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drm/i915/gvt: fix wrong offset when loading RCS mocs
author
Chuanxiao Dong
<chuanxiao.dong@intel.com>
Tue, 21 Mar 2017 01:32:19 +0000
(09:32 +0800)
committer
Zhenyu Wang
<zhenyuw@linux.intel.com>
Tue, 21 Mar 2017 02:45:57 +0000
(10:45 +0800)
Fix the wrong offset of the RCS specific mocs
Fixes:
178657139307
("drm/i915/gvt: vGPU context switch")
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/render.c
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diff --git
a/drivers/gpu/drm/i915/gvt/render.c
b/drivers/gpu/drm/i915/gvt/render.c
index
95ee091
..
0beb835
100644
(file)
--- a/
drivers/gpu/drm/i915/gvt/render.c
+++ b/
drivers/gpu/drm/i915/gvt/render.c
@@
-207,7
+207,7
@@
static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
l3_offset.reg = 0xb020;
for (i = 0; i < 32; i++) {
gen9_render_mocs_L3[i] = I915_READ(l3_offset);
- I915_WRITE(l3_offset, vgpu_vreg(vgpu, offset));
+ I915_WRITE(l3_offset, vgpu_vreg(vgpu,
l3_
offset));
POSTING_READ(l3_offset);
l3_offset.reg += 4;
}