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ddr: imx8m: Add DRAM PLL to generate 1000Mhz output
author
Peng Fan
<peng.fan@nxp.com>
Mon, 30 Dec 2019 01:58:52 +0000
(09:58 +0800)
committer
Stefano Babic
<sbabic@denx.de>
Wed, 8 Jan 2020 12:20:08 +0000
(13:20 +0100)
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
drivers/ddr/imx/imx8m/ddrphy_utils.c
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diff --git
a/drivers/ddr/imx/imx8m/ddrphy_utils.c
b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index
863fb43
..
9ac7ca9
100644
(file)
--- a/
drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/
drivers/ddr/imx/imx8m/ddrphy_utils.c
@@
-106,6
+106,10
@@
int wait_ddrphy_training_complete(void)
void ddrphy_init_set_dfi_clk(unsigned int drate)
{
switch (drate) {
+ case 4000:
+ dram_pll_init(MHZ(1000));
+ dram_disable_bypass();
+ break;
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();