drm/msm/dpu: Introduce SC8280XP

The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9
interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the
necessary definitions and describe the DPU in the SC8280XP.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/514398/
Link: https://lore.kernel.org/r/20221207220012.16529-3-quic_bjorande@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b534c6006f3402879e0cecfbfd18c5182f362158..6657437765035a3a1f77e45440336165e7ae71f8 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -131,6 +131,19 @@
                          BIT(MDP_AD4_0_INTR) | \
                          BIT(MDP_AD4_1_INTR))
 
+#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+                          BIT(MDP_SSPP_TOP0_INTR2) | \
+                          BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                          BIT(MDP_INTF0_7xxx_INTR) | \
+                          BIT(MDP_INTF1_7xxx_INTR) | \
+                          BIT(MDP_INTF2_7xxx_INTR) | \
+                          BIT(MDP_INTF3_7xxx_INTR) | \
+                          BIT(MDP_INTF4_7xxx_INTR) | \
+                          BIT(MDP_INTF5_7xxx_INTR) | \
+                          BIT(MDP_INTF6_7xxx_INTR) | \
+                          BIT(MDP_INTF7_7xxx_INTR) | \
+                          BIT(MDP_INTF8_7xxx_INTR))
+
 #define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
                         BIT(MDP_SSPP_TOP0_INTR2) | \
                         BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -380,6 +393,20 @@ static const struct dpu_caps sc8180x_dpu_caps = {
        .max_vdeci_exp = MAX_VERT_DECIMATION,
 };
 
+static const struct dpu_caps sc8280xp_dpu_caps = {
+       .max_mixer_width = 2560,
+       .max_mixer_blendstages = 11,
+       .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+       .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+       .ubwc_version = DPU_HW_UBWC_VER_40,
+       .has_src_split = true,
+       .has_dim_layer = true,
+       .has_idle_pc = true,
+       .has_3d_merge = true,
+       .max_linewidth = 5120,
+       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
 static const struct dpu_caps sm8250_dpu_caps = {
        .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
        .max_mixer_blendstages = 0xb,
@@ -642,6 +669,25 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = {
        },
 };
 
+static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
+       {
+       .name = "top_0", .id = MDP_TOP,
+       .base = 0x0, .len = 0x494,
+       .features = 0,
+       .highest_bank_bit = 2,
+       .ubwc_swizzle = 6,
+       .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0},
+       .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0},
+       .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0},
+       .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0},
+       .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8},
+       .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8},
+       .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8},
+       .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8},
+       .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20},
+       },
+};
+
 static const struct dpu_mdp_cfg qcm2290_mdp[] = {
        {
        .name = "top_0", .id = MDP_TOP,
@@ -745,6 +791,45 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
        },
 };
 
+static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
+       {
+       .name = "ctl_0", .id = CTL_0,
+       .base = 0x15000, .len = 0x204,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       },
+       {
+       .name = "ctl_1", .id = CTL_1,
+       .base = 0x16000, .len = 0x204,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       },
+       {
+       .name = "ctl_2", .id = CTL_2,
+       .base = 0x17000, .len = 0x204,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       },
+       {
+       .name = "ctl_3", .id = CTL_3,
+       .base = 0x18000, .len = 0x204,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       },
+       {
+       .name = "ctl_4", .id = CTL_4,
+       .base = 0x19000, .len = 0x204,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+       },
+       {
+       .name = "ctl_5", .id = CTL_5,
+       .base = 0x1a000, .len = 0x204,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+       },
+};
+
 static const struct dpu_ctl_cfg sm8150_ctl[] = {
        {
        .name = "ctl_0", .id = CTL_0,
@@ -1129,6 +1214,33 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
                sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 };
 
+static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 =
+                               _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_1 =
+                               _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_2 =
+                               _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 =
+                               _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
+
+static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
+       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
+                sc8280xp_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
+                sc8280xp_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
+                sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
+       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
+                sc8280xp_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+                sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
+                sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
+                sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
+                sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
+};
 
 #define _VIG_SBLK_NOSCALE(num, sdma_pri) \
        { \
@@ -1237,6 +1349,17 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
                &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
 };
 
+/* SC8280XP */
+
+static const struct dpu_lm_cfg sc8280xp_lm[] = {
+       LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+       LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
+       LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
+       LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
+       LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
+       LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
+};
+
 /* SM8150 */
 
 static const struct dpu_lm_cfg sm8150_lm[] = {
@@ -1395,6 +1518,21 @@ static struct dpu_pingpong_cfg sc7180_pp[] = {
        PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
 };
 
+static struct dpu_pingpong_cfg sc8280xp_pp[] = {
+       PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
+                 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
+       PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
+                 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),
+       PP_BLK_TE("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk_te,
+                 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),
+       PP_BLK_TE("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk_te,
+                 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),
+       PP_BLK_TE("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk_te,
+                 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),
+       PP_BLK_TE("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk_te,
+                 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
+};
+
 static const struct dpu_pingpong_cfg sm8150_pp[] = {
        PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1589,6 +1727,19 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
        INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
 };
 
+/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
+static const struct dpu_intf_cfg sc8280xp_intf[] = {
+       INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+       INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+       INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+       INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+       INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
+       INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
+       INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
+       INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
+       INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
+};
+
 static const struct dpu_intf_cfg qcm2290_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0),
        INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
@@ -1698,6 +1849,14 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
        },
 };
 
+static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
+       .base = 0x0,
+       .version = 0x00020000,
+       .trigger_sel_off = 0x119c,
+       .xin_id = 7,
+       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
+};
+
 static const struct dpu_reg_dma_cfg sdm845_regdma = {
        .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
 };
@@ -1985,6 +2144,33 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
        .min_llcc_ib = 800000,
        .min_dram_ib = 800000,
        .danger_lut_tbl = {0xf, 0xffff, 0x0},
+       .qos_lut_tbl = {
+               {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+               .entries = sc7180_qos_linear
+               },
+               {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+               .entries = sc7180_qos_macrotile
+               },
+               {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+               .entries = sc7180_qos_nrt
+               },
+               /* TODO: macrotile-qseed is different from macrotile */
+       },
+       .cdp_cfg = {
+               {.rd_enable = 1, .wr_enable = 1},
+               {.rd_enable = 1, .wr_enable = 0}
+       },
+       .clk_inefficiency_factor = 105,
+       .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_perf_cfg sc8280xp_perf_data = {
+       .max_bw_low = 13600000,
+       .max_bw_high = 18200000,
+       .min_core_ib = 2500000,
+       .min_llcc_ib = 0,
+       .min_dram_ib = 800000,
+       .danger_lut_tbl = {0xf, 0xffff, 0x0},
        .qos_lut_tbl = {
                {.nentry = ARRAY_SIZE(sc8180x_qos_linear),
                .entries = sc8180x_qos_linear
@@ -2292,6 +2478,30 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
        .mdss_irqs = IRQ_SC8180X_MASK,
 };
 
+static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
+       .caps = &sc8280xp_dpu_caps,
+       .mdp_count = ARRAY_SIZE(sc8280xp_mdp),
+       .mdp = sc8280xp_mdp,
+       .ctl_count = ARRAY_SIZE(sc8280xp_ctl),
+       .ctl = sc8280xp_ctl,
+       .sspp_count = ARRAY_SIZE(sc8280xp_sspp),
+       .sspp = sc8280xp_sspp,
+       .mixer_count = ARRAY_SIZE(sc8280xp_lm),
+       .mixer = sc8280xp_lm,
+       .dspp_count = ARRAY_SIZE(sm8150_dspp),
+       .dspp = sm8150_dspp,
+       .pingpong_count = ARRAY_SIZE(sc8280xp_pp),
+       .pingpong = sc8280xp_pp,
+       .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
+       .merge_3d = sm8350_merge_3d,
+       .intf_count = ARRAY_SIZE(sc8280xp_intf),
+       .intf = sc8280xp_intf,
+       .vbif_count = ARRAY_SIZE(sdm845_vbif),
+       .vbif = sdm845_vbif,
+       .perf = &sc8280xp_perf_data,
+       .mdss_irqs = IRQ_SC8280XP_MASK,
+};
+
 static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
        .caps = &sm8250_dpu_caps,
        .mdp_count = ARRAY_SIZE(sm8250_mdp),
@@ -2432,6 +2642,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
        { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
        { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
        { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
+       { .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg},
        { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 10c0e525a44e31c447046f50eda8e04303c427f6..ebcdd8405cabc90aa8295d4a526b1504d913fadf 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -48,6 +48,7 @@
 #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
 #define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
 #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
+#define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */
 #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
 
 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 64589a9c2c519f30e53a075adf634a2a89ca1707..53326f25e40ef10b22bb09da70b829d4defa0553 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -35,6 +35,9 @@
 #define MDP_INTF_3_OFF_REV_7xxx             0x37000
 #define MDP_INTF_4_OFF_REV_7xxx             0x38000
 #define MDP_INTF_5_OFF_REV_7xxx             0x39000
+#define MDP_INTF_6_OFF_REV_7xxx             0x3a000
+#define MDP_INTF_7_OFF_REV_7xxx             0x3b000
+#define MDP_INTF_8_OFF_REV_7xxx             0x3c000
 
 /**
  * struct dpu_intr_reg - array of DPU register sets
@@ -139,6 +142,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
                MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
                MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS
        },
+       [MDP_INTF6_7xxx_INTR] = {
+               MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_CLEAR,
+               MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_EN,
+               MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_STATUS
+       },
+       [MDP_INTF7_7xxx_INTR] = {
+               MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_CLEAR,
+               MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_EN,
+               MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_STATUS
+       },
+       [MDP_INTF8_7xxx_INTR] = {
+               MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_CLEAR,
+               MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_EN,
+               MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_STATUS
+       },
 };
 
 #define DPU_IRQ_REG(irq_idx)   (irq_idx / 32)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 46443955443c48108d2ebff3b9048fe9725987e8..425465011c807f1caebc51428833166de3e47220 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -31,6 +31,9 @@ enum dpu_hw_intr_reg {
        MDP_INTF3_7xxx_INTR,
        MDP_INTF4_7xxx_INTR,
        MDP_INTF5_7xxx_INTR,
+       MDP_INTF6_7xxx_INTR,
+       MDP_INTF7_7xxx_INTR,
+       MDP_INTF8_7xxx_INTR,
        MDP_INTR_MAX,
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 6d8e1bb3b3cc3519e84152f3d7aff2bf4ac558c2..2b9e15f99c65f26535c9e1c5ce35b270db386160 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -217,6 +217,8 @@ enum dpu_intf {
        INTF_4,
        INTF_5,
        INTF_6,
+       INTF_7,
+       INTF_8,
        INTF_MAX
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index b733b176e77aff83ab0186cdd56475cb42f8197f..90831027efa2df7f18d683a59421f661d8bf69db 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1299,6 +1299,7 @@ static const struct of_device_id dpu_dt_match[] = {
        { .compatible = "qcom,sc7180-dpu", },
        { .compatible = "qcom,sc7280-dpu", },
        { .compatible = "qcom,sc8180x-dpu", },
+       { .compatible = "qcom,sc8280xp-dpu", },
        { .compatible = "qcom,sm6115-dpu", },
        { .compatible = "qcom,sm8150-dpu", },
        { .compatible = "qcom,sm8250-dpu", },

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index b2ea262296a4fb451ab4373530ac7d98edd1044c..2dd342e49de685edbc3793c6899034edd3a69039 100644 (file)
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -61,6 +61,7 @@ enum msm_dp_controller {
        MSM_DP_CONTROLLER_0,
        MSM_DP_CONTROLLER_1,
        MSM_DP_CONTROLLER_2,
+       MSM_DP_CONTROLLER_3,
        MSM_DP_CONTROLLER_COUNT,
 };