Merge tag 'signed-efi-2018.05' of git://github.com/agraf/u-boot
authorTom Rini <trini@konsulko.com>
Mon, 23 Apr 2018 20:17:36 +0000 (16:17 -0400)
committerTom Rini <trini@konsulko.com>
Mon, 23 Apr 2018 20:17:36 +0000 (16:17 -0400)
Patch queue for efi - 2018-04-23

Some last minute fixes for 2018.05. Most of them are minor fixes. On
top we have some functional improvements for the device path logic
which should also help us be more compatible.

17 files changed:
arch/arm/dts/uniphier-v7-u-boot.dtsi
arch/arm/mach-zynq/Kconfig
arch/arm/mach-zynq/include/mach/nand.h [deleted file]
board/xilinx/zynq/board.c
board/xilinx/zynqmp/zynqmp.c
cmd/clk.c
configs/zynq_zc770_xm011_x16_defconfig
drivers/clk/uniphier/Kconfig
drivers/mmc/meson_gx_mmc.c
drivers/mmc/mmc.c
drivers/mmc/renesas-sdhi.c
drivers/mmc/tmio-common.c
drivers/mmc/uniphier-sd.c
drivers/mtd/nand/zynq_nand.c
drivers/watchdog/cdns_wdt.c
include/configs/uniphier.h
include/configs/zynq-common.h

index 0094a45..9459bf0 100644 (file)
                        u-boot,dm-pre-reloc;
                };
 
-               mioctrl@59810000 {
-                       u-boot,dm-pre-reloc;
-
-                       clock {
-                               u-boot,dm-pre-reloc;
-                       };
-               };
-
-               sdctrl@59810000 {
-                       u-boot,dm-pre-reloc;
-
-                       clock {
-                               u-boot,dm-pre-reloc;
-                       };
-               };
-
                soc-glue@5f800000 {
                        u-boot,dm-pre-reloc;
 
index 8772904..1352359 100644 (file)
@@ -36,6 +36,7 @@ config ZYNQ_DDRC_INIT
          want to skip ddr init and this option is useful for it.
 
 config SYS_BOARD
+       string "Board name"
        default "zynq"
 
 config SYS_VENDOR
diff --git a/arch/arm/mach-zynq/include/mach/nand.h b/arch/arm/mach-zynq/include/mach/nand.h
deleted file mode 100644 (file)
index 61ef45f..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (C) 2017 National Instruments Corp.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <nand.h>
-
-void zynq_nand_init(void);
index 838ac0f..2f4679e 100644 (file)
@@ -184,7 +184,8 @@ int dram_init(void)
 #else
 int dram_init(void)
 {
-       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+                                   CONFIG_SYS_SDRAM_SIZE);
 
        zynq_ddrc_init();
 
index 0d1bd54..3c4cf80 100644 (file)
@@ -377,7 +377,8 @@ int dram_init(void)
 #else
 int dram_init(void)
 {
-       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+                                   CONFIG_SYS_SDRAM_SIZE);
 
        return 0;
 }
index 6d3d46a..52b2540 100644 (file)
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -16,7 +16,15 @@ int __weak soc_clk_dump(void)
 static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
                       char *const argv[])
 {
-       return soc_clk_dump();
+       int ret;
+
+       ret = soc_clk_dump();
+       if (ret < 0) {
+               printf("Clock dump error %d\n", ret);
+               ret = CMD_RET_FAILURE;
+       }
+
+       return ret;
 }
 
 static cmd_tbl_t cmd_clk_sub[] = {
index b53ca3d..036b73f 100644 (file)
@@ -29,11 +29,11 @@ CONFIG_CMD_CACHE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQPL=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
-CONFIG_DM_MMC=y
 CONFIG_NAND=y
 CONFIG_NAND_ZYNQ=y
 CONFIG_DEBUG_UART_ZYNQ=y
index 3666d84..a26ca8c 100644 (file)
@@ -2,7 +2,6 @@ config CLK_UNIPHIER
        def_bool y
        depends on ARCH_UNIPHIER
        select CLK
-       select SPL_CLK if SPL
        help
          Support for clock controllers on UniPhier SoCs.
          Say Y if you want to control clocks provided by System Control
index a2cd5d3..454593e 100644 (file)
@@ -35,6 +35,9 @@ static void meson_mmc_config_clock(struct mmc *mmc)
        uint32_t meson_mmc_clk = 0;
        unsigned int clk, clk_src, clk_div;
 
+       if (!mmc->clock)
+               return;
+
        /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
        if (mmc->clock > 16000000) {
                clk = SD_EMMC_CLKSRC_DIV2;
index c930893..f72b80c 100644 (file)
@@ -1334,7 +1334,7 @@ static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
        return 0;
 }
 
-int sd_select_bus_width(struct mmc *mmc, int w)
+static int sd_select_bus_width(struct mmc *mmc, int w)
 {
        int err;
        struct mmc_cmd cmd;
index 56a43ca..8e49b2f 100644 (file)
@@ -330,8 +330,10 @@ static const struct udevice_id renesas_sdhi_match[] = {
 
 static int renesas_sdhi_probe(struct udevice *dev)
 {
+       struct tmio_sd_priv *priv = dev_get_priv(dev);
        u32 quirks = dev_get_driver_data(dev);
        struct fdt_resource reg_res;
+       struct clk clk;
        DECLARE_GLOBAL_DATA_PTR;
        int ret;
 
@@ -348,6 +350,27 @@ static int renesas_sdhi_probe(struct udevice *dev)
                        quirks |= TMIO_SD_CAP_16BIT;
        }
 
+       ret = clk_get_by_index(dev, 0, &clk);
+       if (ret < 0) {
+               dev_err(dev, "failed to get host clock\n");
+               return ret;
+       }
+
+       /* set to max rate */
+       priv->mclk = clk_set_rate(&clk, ULONG_MAX);
+       if (IS_ERR_VALUE(priv->mclk)) {
+               dev_err(dev, "failed to set rate for host clock\n");
+               clk_free(&clk);
+               return priv->mclk;
+       }
+
+       ret = clk_enable(&clk);
+       clk_free(&clk);
+       if (ret) {
+               dev_err(dev, "failed to enable host clock\n");
+               return ret;
+       }
+
        ret = tmio_sd_probe(dev, quirks);
 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
        if (!ret)
index 5f1c9c0..4ea6612 100644 (file)
@@ -713,7 +713,6 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
        struct tmio_sd_priv *priv = dev_get_priv(dev);
        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
        fdt_addr_t base;
-       struct clk clk;
        int ret;
 
        base = devfdt_get_addr(dev);
@@ -728,27 +727,6 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
        device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
 #endif
 
-       ret = clk_get_by_index(dev, 0, &clk);
-       if (ret < 0) {
-               dev_err(dev, "failed to get host clock\n");
-               return ret;
-       }
-
-       /* set to max rate */
-       priv->mclk = clk_set_rate(&clk, ULONG_MAX);
-       if (IS_ERR_VALUE(priv->mclk)) {
-               dev_err(dev, "failed to set rate for host clock\n");
-               clk_free(&clk);
-               return priv->mclk;
-       }
-
-       ret = clk_enable(&clk);
-       clk_free(&clk);
-       if (ret) {
-               dev_err(dev, "failed to enable host clock\n");
-               return ret;
-       }
-
        ret = mmc_of_parse(dev, &plat->cfg);
        if (ret < 0) {
                dev_err(dev, "failed to parse host caps\n");
index 47379b0..61f8da4 100644 (file)
@@ -32,6 +32,35 @@ static const struct udevice_id uniphier_sd_match[] = {
 
 static int uniphier_sd_probe(struct udevice *dev)
 {
+       struct tmio_sd_priv *priv = dev_get_priv(dev);
+#ifndef CONFIG_SPL_BUILD
+       struct clk clk;
+       int ret;
+
+       ret = clk_get_by_index(dev, 0, &clk);
+       if (ret < 0) {
+               dev_err(dev, "failed to get host clock\n");
+               return ret;
+       }
+
+       /* set to max rate */
+       priv->mclk = clk_set_rate(&clk, ULONG_MAX);
+       if (IS_ERR_VALUE(priv->mclk)) {
+               dev_err(dev, "failed to set rate for host clock\n");
+               clk_free(&clk);
+               return priv->mclk;
+       }
+
+       ret = clk_enable(&clk);
+       clk_free(&clk);
+       if (ret) {
+               dev_err(dev, "failed to enable host clock\n");
+               return ret;
+       }
+#else
+       priv->mclk = 100000000;
+#endif
+
        return tmio_sd_probe(dev, 0);
 }
 
index 6494196..2d4e8b4 100644 (file)
@@ -1006,7 +1006,7 @@ static int zynq_nand_device_ready(struct mtd_info *mtd)
        return 0;
 }
 
-int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 {
        struct zynq_nand_info *xnand;
        struct mtd_info *mtd;
@@ -1025,7 +1025,7 @@ int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
        }
 
        xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
-       mtd = get_nand_dev_by_index(0);
+       mtd = nand_to_mtd(nand_chip);
 
        nand_chip->priv = xnand;
        mtd->priv = nand_chip;
@@ -1192,14 +1192,12 @@ fail:
        return err;
 }
 
-#ifdef CONFIG_SYS_NAND_SELF_INIT
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
-void __weak board_nand_init(void)
+void board_nand_init(void)
 {
        struct nand_chip *nand = &nand_chip[0];
 
        if (zynq_nand_init(nand, 0))
                puts("ZYNQ NAND init failed\n");
 }
-#endif
index 71733cf..c43f7e8 100644 (file)
@@ -25,7 +25,6 @@ struct cdns_regs {
 struct cdns_wdt_priv {
        bool rst;
        u32 timeout;
-       void __iomem *reg;
        struct cdns_regs *regs;
 };
 
@@ -224,12 +223,8 @@ static int cdns_wdt_stop(struct udevice *dev)
  */
 static int cdns_wdt_probe(struct udevice *dev)
 {
-       struct cdns_wdt_priv *priv = dev_get_priv(dev);
-
        debug("%s: Probing wdt%u\n", __func__, dev->seq);
 
-       priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs));
-
        cdns_wdt_stop(dev);
 
        return 0;
index 1b4140d..c39f13b 100644 (file)
@@ -33,7 +33,7 @@
 
 #define CONFIG_SYS_MAX_FLASH_SECT      256
 #define CONFIG_SYS_MONITOR_BASE                0
-#define CONFIG_SYS_MONITOR_LEN         0x00080000      /* 512KB */
+#define CONFIG_SYS_MONITOR_LEN         0x00090000      /* 576KB */
 #define CONFIG_SYS_FLASH_BASE          0
 
 /*
                "setexpr tmp_addr $nor_base + 0x70000 && " \
                "tftpboot $tmp_addr $third_image\0" \
        "emmcupdate=mmcsetn &&"                                 \
+               "mmc dev $mmc_first_dev &&"                     \
                "mmc partconf $mmc_first_dev 0 1 1 &&"          \
                "tftpboot $second_image && " \
                "mmc write $loadaddr 0 100 && " \
 #define CONFIG_SPL_TEXT_BASE           0x00100000
 #endif
 
-#define CONFIG_SPL_STACK               (0x00100000)
+#define CONFIG_SPL_STACK               (0x00200000)
 
 #define CONFIG_SYS_NAND_U_BOOT_OFFS            0x20000
 
index ae82a7a..baad8db 100644 (file)
 #endif
 
 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE                        (128 << 10)
+#ifndef CONFIG_ENV_SIZE
+# define CONFIG_ENV_SIZE                       (128 << 10)
+#endif
 
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 /* Environment */
 #ifndef CONFIG_ENV_IS_NOWHERE
 # define CONFIG_ENV_SECT_SIZE          CONFIG_ENV_SIZE
-# define CONFIG_ENV_OFFSET             0xE0000
+# ifndef CONFIG_ENV_OFFSET
+#  define CONFIG_ENV_OFFSET            0xE0000
+# endif
 #endif
 
 /* enable preboot to be loaded before CONFIG_BOOTDELAY */