arm, am33xx: move rtc32k_enable() to common place

move rtc32k_enable() to common place so all am33xx boards can use it.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 885fb2d..d3b3612 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -149,3 +149,21 @@ int arch_misc_init(void)
 #endif
        return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+void rtc32k_enable(void)
+{
+       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+       /*
+        * Unlock the RTC's registers.  For more details please see the
+        * RTC_SS section of the TRM.  In order to unlock we need to
+        * write these specific values (keys) in this order.
+        */
+       writel(0x83e70b13, &rtc->kick0r);
+       writel(0x95a4f1e0, &rtc->kick1r);
+
+       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+       writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+#endif

diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index fedc674..6cce5a5 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -41,4 +41,6 @@ void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
                        u32 size);
 void omap_nand_switch_ecc(uint32_t, uint32_t);
+
+void rtc32k_enable(void);
 #endif

diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 826cead..3e9e25f 100644 (file)
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -51,22 +51,6 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 #define UART_CLK_RUNNING_MASK  0x1
 #define UART_SMART_IDLE_EN     (0x1 << 0x3)
 
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
        .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,

diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 93c611d..281f699 100644 (file)
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -59,22 +59,6 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 /* DDR RAM defines */
 #define DDR_CLK_MHZ            303 /* DDR_DPLL_MULT value */
 
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = MT41J256M8HX15E_RD_DQS,
        .datawdsratio0 = MT41J256M8HX15E_WR_DQS,

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 06e8f07..75f129e 100644 (file)
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -132,22 +132,6 @@ static int read_eeprom(void)
 #define UART_CLK_RUNNING_MASK  0x1
 #define UART_SMART_IDLE_EN     (0x1 << 0x3)
 
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr2_data = {
        .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
                          (MT47H128M16RT25E_RD_DQS<<20) |

diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 4759b16..38a6ced 100644 (file)
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -48,22 +48,6 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 #define UART_CLK_RUNNING_MASK  0x1
 #define UART_SMART_IDLE_EN     (0x1 << 0x3)
 
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static void uart_enable(void)
 {
        u32 regVal;