clk: samsung: exynos5422: fix MFC clock hierarchy parent

Proper source for MFC block is mout_user_aclk333 (in datasheet named
USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX.

Change-id: I291a53c5e7668eed0a83eed04b67c4a139852fa0
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 462aaeee0f1fd254096bd3868cf36a30644e42e0..14bafb39ceb85224d4e2bbe2da22bb028af21b86 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -929,7 +929,7 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
                        GATE_BUS_TOP, 13, 0, 0),
        GATE(0, "aclk166", "mout_user_aclk166",
                        GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
-       GATE(0, "aclk333", "mout_aclk333",
+       GATE(0, "aclk333", "mout_user_aclk333",
                        GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
        GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
                        GATE_BUS_TOP, 16, 0, 0),