"ptp_ref",
"stmmaceth",
"pclk",
- "gtxc";
+ "gtxc",
+ "rmii_rtx";
clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
<&clkgen JH7110_U0_GMAC5_CLK_TX>,
<&clkgen JH7110_GMAC0_PTP>,
<&clkgen JH7110_U0_GMAC5_CLK_AHB>,
<&clkgen JH7110_U0_GMAC5_CLK_AXI>,
- <&clkgen JH7110_GMAC0_GTXC>;
+ <&clkgen JH7110_GMAC0_GTXC>,
+ <&clkgen JH7110_GMAC0_RMII_RTX>;
resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
<&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
reset-names = "ahb", "stmmaceth";
"ptp_ref",
"stmmaceth",
"pclk",
- "gtxc";
+ "gtxc",
+ "rmii_rtx";
clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
<&clkgen JH7110_GMAC5_CLK_TX>,
<&clkgen JH7110_GMAC5_CLK_PTP>,
<&clkgen JH7110_GMAC5_CLK_AHB>,
<&clkgen JH7110_GMAC5_CLK_AXI>,
- <&clkgen JH7110_GMAC1_GTXC>;
+ <&clkgen JH7110_GMAC1_GTXC>,
+ <&clkgen JH7110_GMAC1_RMII_RTX>;
resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
<&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
reset-names = "ahb", "stmmaceth";
struct clk *clk_tx;
struct clk *clk_gtx;
struct clk *clk_gtxc;
+ struct clk *clk_rmii_rtx;
};
static void starfive_eth_fix_mac_speed(void *priv, unsigned int speed)
err = clk_set_rate(dwmac->clk_gtx, rate);
if (err < 0)
dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
+
+ err = clk_set_rate(dwmac->clk_rmii_rtx, rate);
+ if (err < 0)
+ dev_err(dwmac->dev, "failed to set rtx rate %lu\n", rate);
}
static const struct of_device_id starfive_eth_plat_match[] = {
goto disable_gtx;
}
+ dwmac->clk_rmii_rtx = devm_clk_get(&pdev->dev, "rmii_rtx");
+ if (IS_ERR(dwmac->clk_rmii_rtx)) {
+ err = PTR_ERR(dwmac->clk_rmii_rtx);
+ goto disable_gtx;
+ }
+
err = clk_prepare_enable(dwmac->clk_gtxc);
if (err < 0)
goto disable_gtx;