const void *Decoder);
static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address,
+ const void *Decoder, bool isLoad,
+ DecodeFunc DecodeSX) {
+ unsigned sx = fieldFromInstruction(insn, 48, 7);
+
+ DecodeStatus status;
+ if (isLoad) {
+ status = DecodeSX(MI, sx, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+ }
+
+ status = DecodeAS(MI, insn, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+
+ if (!isLoad) {
+ status = DecodeSX(MI, sx, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+ }
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass);
return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);
}
+static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder) {
+ return DecodeMemAS(Inst, insn, Address, Decoder, true,
+ DecodeI64RegisterClass);
+}
+
+static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder) {
+ return DecodeMemAS(Inst, insn, Address, Decoder, false,
+ DecodeI64RegisterClass);
+}
+
static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,
const void *Decoder, bool isImmOnly, bool isUImm,
DecodeFunc DecodeSX) {
}
}
-void VEInstPrinter::printMemASOperand(const MCInst *MI, int OpNum,
- const MCSubtargetInfo &STI,
- raw_ostream &O, const char *Modifier) {
+void VEInstPrinter::printMemASOperandHM(const MCInst *MI, int OpNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O, const char *Modifier) {
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
printOperand(MI, OpNum, STI, O);
return;
}
- const MCOperand &MO = MI->getOperand(OpNum + 1);
- if (!MO.isImm() || MO.getImm() != 0) {
+ if (MI->getOperand(OpNum + 1).isImm() &&
+ MI->getOperand(OpNum + 1).getImm() == 0) {
+ // don't print "+0"
+ } else {
printOperand(MI, OpNum + 1, STI, O);
}
O << "(";
- printOperand(MI, OpNum, STI, O);
+ if (MI->getOperand(OpNum).isReg())
+ printOperand(MI, OpNum, STI, O);
O << ")";
}
void printMemASOperandRRM(const MCInst *MI, int OpNum,
const MCSubtargetInfo &STI, raw_ostream &OS,
const char *Modifier = nullptr);
- void printMemASOperand(const MCInst *MI, int OpNum,
- const MCSubtargetInfo &STI, raw_ostream &OS,
- const char *Modifier = nullptr);
+ void printMemASOperandHM(const MCInst *MI, int OpNum,
+ const MCSubtargetInfo &STI, raw_ostream &OS,
+ const char *Modifier = nullptr);
void printMImmOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
raw_ostream &OS);
void printCCOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
list<dag> pattern = []>
: RM<opVal, outs, ins, asmstr, pattern>;
+// RRMHM type is to load/store host memory
+// It is similar to RRM and not use sy.
+class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,
+ list<dag> pattern = []>
+ : RRM<opVal, outs, ins, asmstr, pattern> {
+ bits<2> ry = 0;
+ let cy = 0;
+ let sy{6-2} = 0;
+ let sy{1-0} = ry;
+}
+
//-----------------------------------------------------------------------------
// Section 5.3 CF Type
//
.addImm(0)
.addImm(0)
.addImm(0x13b);
- BuildMI(BB, dl, TII.get(VE::SHMri))
+ BuildMI(BB, dl, TII.get(VE::SHMLri))
.addReg(VE::SX61)
.addImm(0)
.addReg(VE::SX63);
- BuildMI(BB, dl, TII.get(VE::SHMri))
+ BuildMI(BB, dl, TII.get(VE::SHMLri))
.addReg(VE::SX61)
.addImm(8)
.addReg(VE::SX8);
- BuildMI(BB, dl, TII.get(VE::SHMri))
+ BuildMI(BB, dl, TII.get(VE::SHMLri))
.addReg(VE::SX61)
.addImm(16)
.addReg(VE::SX11);
}
}]>;
+//===----------------------------------------------------------------------===//
// Addressing modes.
// SX-Aurora has following fields.
// sz: register or 0
// AS format:
// MEMriASX, MEMziASX : simple AS format
// MEMriRRM, MEMziRRM : AS format in RRM format
-// well be added later.
+// MEMriHM, MEMziHM : AS format in RRM format for host memory access
+//===----------------------------------------------------------------------===//
// DAG selections for both ASX and AS formats.
def ADDRrri : ComplexPattern<iPTR, 3, "selectADDRrri", [frameindex], []>;
let ParserMatchClass = VEMEMziAsmOperand;
}
-def MEMASri : Operand<iPTR> {
- let PrintMethod = "printMemASOperand";
+// 3. AS HM style assembly instruction format:
+def MEMriHM : Operand<iPTR> {
+ let PrintMethod = "printMemASOperandHM";
let MIOperandInfo = (ops ptr_rc, i32imm);
let ParserMatchClass = VEMEMriAsmOperand;
}
+def MEMziHM : Operand<iPTR> {
+ let PrintMethod = "printMemASOperandHM";
+ let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);
+ let ParserMatchClass = VEMEMziAsmOperand;
+}
+
+//===----------------------------------------------------------------------===//
+// Other operands.
+//===----------------------------------------------------------------------===//
// Branch targets have OtherVT type.
def brtarget32 : Operand<OtherVT> {
!strconcat(opcStr, " $sx, $sy, $sz")>;
}
+// Multiclass for LHM instruction.
+let mayLoad = 1, hasSideEffects = 0 in
+multiclass LHMm<string opcStr, bits<8> opc, RegisterClass RC> {
+ def ri : RRMHM<opc, (outs RC:$dest), (ins MEMriHM:$addr),
+ !strconcat(opcStr, " $dest, $addr")>;
+ let cz = 0 in
+ def zi : RRMHM<opc, (outs RC:$dest), (ins MEMziHM:$addr),
+ !strconcat(opcStr, " $dest, $addr")>;
+}
+
+// Multiclass for SHM instruction.
+let mayStore = 1, hasSideEffects = 0 in
+multiclass SHMm<string opcStr, bits<8> opc, RegisterClass RC> {
+ def ri : RRMHM<opc, (outs), (ins MEMriHM:$addr, RC:$sx),
+ !strconcat(opcStr, " $sx, $addr")>;
+ let cz = 0 in
+ def zi : RRMHM<opc, (outs), (ins MEMziHM:$addr, RC:$sx),
+ !strconcat(opcStr, " $sx, $addr")>;
+}
+
//===----------------------------------------------------------------------===//
// Instructions
//
// Section 8.19.12 - FIDCR (Fetch & Increment/Decrement CR)
defm FIDCR : FIDCRm<"fidcr", 0x51, I64>;
-let cx = 0, cy = 0, cz = 1, hasSideEffects = 0 in {
-let sy = 3 in
-def SHMri : RM<
- 0x31, (outs), (ins MEMASri:$addr, I64:$sx),
- "shm.l $sx, $addr">;
-}
+//-----------------------------------------------------------------------------
+// Section 8.20 - Host Memory Access Instructions
+//-----------------------------------------------------------------------------
+
+// Section 8.20.1 - LHM (Load Host Memory)
+let ry = 3, DecoderMethod = "DecodeLoadASI64" in
+defm LHML : LHMm<"lhm.l", 0x21, I64>;
+let ry = 2, DecoderMethod = "DecodeLoadASI64" in
+defm LHMW : LHMm<"lhm.w", 0x21, I64>;
+let ry = 1, DecoderMethod = "DecodeLoadASI64" in
+defm LHMH : LHMm<"lhm.h", 0x21, I64>;
+let ry = 0, DecoderMethod = "DecodeLoadASI64" in
+defm LHMB : LHMm<"lhm.b", 0x21, I64>;
+
+// Section 8.20.2 - SHM (Store Host Memory)
+let ry = 3, DecoderMethod = "DecodeStoreASI64" in
+defm SHML : SHMm<"shm.l", 0x31, I64>;
+let ry = 2, DecoderMethod = "DecodeStoreASI64" in
+defm SHMW : SHMm<"shm.w", 0x31, I64>;
+let ry = 1, DecoderMethod = "DecodeStoreASI64" in
+defm SHMH : SHMm<"shm.h", 0x31, I64>;
+let ry = 0, DecoderMethod = "DecodeStoreASI64" in
+defm SHMB : SHMm<"shm.b", 0x31, I64>;
//===----------------------------------------------------------------------===//
// Instructions for CodeGenOnly
--- /dev/null
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: lhm.l %s20, 20(%s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x03,0x14,0x21]
+lhm.l %s20, 20(%s11)
+
+# CHECK-INST: lhm.w %s20, 8192()
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x02,0x14,0x21]
+lhm.w %s20, 8192()
+
+# CHECK-INST: lhm.h %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x01,0x14,0x21]
+lhm.h %s20, (%s11)
+
+# CHECK-INST: lhm.b %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x00,0x14,0x21]
+lhm.b %s20, %s11
--- /dev/null
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: shm.l %s20, 20(%s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x03,0x14,0x31]
+shm.l %s20, 20(%s11)
+
+# CHECK-INST: shm.w %s20, 8192()
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x02,0x14,0x31]
+shm.w %s20, 8192()
+
+# CHECK-INST: shm.h %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x01,0x14,0x31]
+shm.h %s20, (%s11)
+
+# CHECK-INST: shm.b %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x00,0x14,0x31]
+shm.b %s20, %s11