// ldr ip, [pc, #...]
// blx ip
- { // NOLINT
- // The two instructions (ldr and blx) could be separated by a constant
- // pool and the code would still work. The issue comes from the
- // patching code which expect the ldr to be just above the blx.
- BlockConstPoolScope block_const_pool(this);
+ // The two instructions (ldr and blx) could be separated by a constant
+ // pool and the code would still work. The issue comes from the
+ // patching code which expect the ldr to be just above the blx.
+ { BlockConstPoolScope block_const_pool(this);
// Statement positions are expected to be recorded when the target
// address is loaded. The mov method will automatically record
// positions when pc is the target, since this is not the case here
#endif
// New scope to get automatic timing calculation.
- { // NOLINT
- HistogramTimerScope codegen_timer(&Counters::code_generation);
+ { HistogramTimerScope codegen_timer(&Counters::code_generation);
CodeGenState state(this);
// Entry:
__ j(zero, &runtime_call_clear_stack);
#ifdef DEBUG
// Check that the layout of cache elements match expectations.
- { // NOLINT - doesn't like a single brace on a line.
- TranscendentalCache::Element test_elem[2];
+ { TranscendentalCache::Element test_elem[2];
char* elem_start = reinterpret_cast<char*>(&test_elem[0]);
char* elem2_start = reinterpret_cast<char*>(&test_elem[1]);
char* elem_in0 = reinterpret_cast<char*>(&(test_elem[0].in[0]));
#endif
// New scope to get automatic timing calculation.
- { // NOLINT
- HistogramTimerScope codegen_timer(&Counters::code_generation);
+ { HistogramTimerScope codegen_timer(&Counters::code_generation);
CodeGenState state(this);
// Entry: