block: Move ceva driver to DM

This patch also includes ARM64 zynqmp changes:
- Remove platform non DM initialization
- Remove hardcoded sata base address

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 5908c50..041b43c 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -18,8 +18,6 @@
 
 #define ARASAN_NAND_BASEADDR   0xFF100000
 
-#define ZYNQMP_SATA_BASEADDR   0xFD0C0000
-
 #define ZYNQMP_USB0_XHCI_BASEADDR      0xFE200000
 #define ZYNQMP_USB1_XHCI_BASEADDR      0xFE300000
 

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index cef1f6a..a23c38a 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -311,17 +311,6 @@ void reset_cpu(ulong addr)
 {
 }
 
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void scsi_init(void)
-{
-#if defined(CONFIG_SATA_CEVA)
-       init_sata(0);
-#endif
-       ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
-       scsi_scan(1);
-}
-#endif
-
 int board_late_init(void)
 {
        u32 reg = 0;

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index f261e22..b223e11 100644 (file)
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -42,6 +42,8 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 021e0ff..9f2df49 100644 (file)
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -34,6 +34,8 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 34062bd..b2b1720 100644 (file)
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -34,6 +34,8 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 7b82ba6..88e66e2 100644 (file)
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -39,4 +39,13 @@ config BLOCK_CACHE
 
 menu "SATA/SCSI device support"
 
+config SATA_CEVA
+       bool "Ceva Sata controller"
+       depends on AHCI
+       depends on DM_SCSI
+       help
+         This option enables Ceva Sata controller hard IP available on Xilinx
+         ZynqMP. Support up to 2 external devices. Complient with SATA 3.1 and
+         AHCI 1.3 specifications with hot-plug detect feature.
+
 endmenu

diff --git a/drivers/block/sata_ceva.c b/drivers/block/sata_ceva.c
index dcc3b90..9b54664 100644 (file)
--- a/drivers/block/sata_ceva.c
+++ b/drivers/block/sata_ceva.c
@@ -5,6 +5,7 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
 #include <netdev.h>
 #include <ahci.h>
 #include <scsi.h>
@@ -73,10 +74,9 @@
 #define DRV_NAME       "ahci-ceva"
 #define CEVA_FLAG_BROKEN_GEN2  1
 
-int init_sata(int dev)
+static int ceva_init_sata(ulong mmio)
 {
        ulong tmp;
-       ulong mmio = ZYNQMP_SATA_BASEADDR;
        int i;
 
        /*
@@ -111,3 +111,40 @@ int init_sata(int dev)
        }
        return 0;
 }
+
+static int sata_ceva_probe(struct udevice *dev)
+{
+       struct scsi_platdata *plat = dev_get_platdata(dev);
+
+       ceva_init_sata(plat->base);
+       return 0;
+}
+
+static const struct udevice_id sata_ceva_ids[] = {
+       { .compatible = "ceva,ahci-1v84" },
+       { }
+};
+
+static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
+{
+       struct scsi_platdata *plat = dev_get_platdata(dev);
+
+       plat->base = dev_get_addr(dev);
+       if (plat->base == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       /* Hardcode number for ceva sata controller */
+       plat->max_lun = 1; /* Actually two but untested */
+       plat->max_id = 2;
+
+       return 0;
+}
+
+U_BOOT_DRIVER(ceva_host_blk) = {
+       .name = "ceva_sata",
+       .id = UCLASS_SCSI,
+       .of_match = sata_ceva_ids,
+       .probe = sata_ceva_probe,
+       .ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
+       .platdata_auto_alloc_size = sizeof(struct scsi_platdata),
+};

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index d480990..fb4f6d6 100644 (file)
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -181,7 +181,6 @@
 #ifdef CONFIG_SATA_CEVA
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
-#define CONFIG_SCSI_AHCI_PLAT
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID    2
 #define CONFIG_SYS_SCSI_MAX_LUN                1
 #define CONFIG_SYS_SCSI_MAX_DEVICE     (CONFIG_SYS_SCSI_MAX_SCSI_ID * \

diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index d0ce768..3a572b7 100644 (file)
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -16,7 +16,6 @@
 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ     52000000
 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ     (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
 #define CONFIG_ZYNQ_EEPROM
-#define CONFIG_SATA_CEVA
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
                                 ZYNQMP_USB1_XHCI_BASEADDR}
 

diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index adf2321..8d018da 100644 (file)
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -41,8 +41,6 @@
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 
-#define CONFIG_SATA_CEVA
-
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
 
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1