drm/amd/display: Only clear symclk otg flag for HDMI

[ Upstream commit dff45f03f508c92cd8eb2050e27b726726b8ae0b ]

[Description]
There is a corner case where the symclk otg flag is cleared
when disabling the phantom pipe for subvp (because the phantom
and main pipe share the same link). This is undesired because
we need the maintain the correct symclk otg flag state for
the main pipe.

For now only clear the flag only for HDMI signal type, since
it's only set for HDMI signal type (phantom is virtual). The
ideal solution is to not clear it if the stream is phantom but
currently there's a bug that doesn't allow us to do this. Once
this issue is fixed the proper fix can be implemented.

Reviewed-by: Samson Tam <samson.tam@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 7fbbad6..251dd80 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2124,7 +2124,8 @@ static void dce110_reset_hw_ctx_wrap(
                                BREAK_TO_DEBUGGER();
                        }
                        pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
-                       pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+                       if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))
+                               pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
                        pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
                                        pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 13ccb57..db1d7be 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1054,7 +1054,8 @@ static void dcn10_reset_back_end_for_pipe(
                if (pipe_ctx->stream_res.tg->funcs->set_drr)
                        pipe_ctx->stream_res.tg->funcs->set_drr(
                                        pipe_ctx->stream_res.tg, NULL);
-               pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+               if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+                       pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
        }
 
        for (i = 0; i < dc->res_pool->pipe_count; i++)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 2c4bcbc..1e38037 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2533,7 +2533,8 @@ static void dcn20_reset_back_end_for_pipe(
                 * the case where the same symclk is shared across multiple otg
                 * instances
                 */
-               link->phy_state.symclk_ref_cnts.otg = 0;
+               if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+                       link->phy_state.symclk_ref_cnts.otg = 0;
                if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
                        link_hwss->disable_link_output(link,
                                        &pipe_ctx->link_res, pipe_ctx->stream->signal);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 2a7f476..22da200 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -523,7 +523,8 @@ static void dcn31_reset_back_end_for_pipe(
        if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
                pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
                                pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
-       pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+       if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+               pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
 
        if (pipe_ctx->stream_res.tg->funcs->set_drr)
                pipe_ctx->stream_res.tg->funcs->set_drr(