hdmirx: update vb phy setting [1/1]

PD#SWPL-6234

Problem:
flash line in the screen when HDMI connect iTV IV3010 box.

Solution:
1.update phy low frequency setting;
2.optimzie pll init sequence to save some detection time;
3.update verB pll setting(0323);

Verify:
TL1

Change-Id: I71225b06f02e4888ce093780a2beb0a381986293
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
index 1a4c2b0..511bd2a 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
@@ -34,7 +34,7 @@
 #include "hdmi_rx_edid.h"
 
 
-#define RX_VER0 "ver.2019-03-13"
+#define RX_VER0 "ver.2019-03-25"
 /*
  *
  *

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
index 9a48d1a..871b75f 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
@@ -96,6 +96,7 @@ int ignore_sscp_charerr = 1;
 int ignore_sscp_tmds = 1;
 int find_best_eq;
 int eq_try_cnt = 20;
+int pll_rst_max = 10;
 /*------------------------variable define end------------------------------*/
 
 static int check_regmap_flag(unsigned int addr)
@@ -998,6 +999,13 @@ int rx_set_audio_param(uint32_t param)
 }
 EXPORT_SYMBOL(rx_set_audio_param);
 
+bool is_tl1_former(void)
+{
+       if (is_meson_tl1_cpu() &&
+               is_meson_rev_a())
+               return 1;
+       return 0;
+}
 /*
  * rx_get_hdmi5v_sts - get current pwr5v status on all ports
  */
@@ -3345,10 +3353,10 @@ void aml_phy_switch_port(void)
 static const uint32_t phy_misci[][4] = {
                /* 0xd7                 0xd8            0xe0            0xe1 */
        {       /* 24~45M */
-               0x3003707f,     0x00400080,     0x02218000,     0x00000010,
+               0x3003707f,     0x00000080,     0x02218000,     0x00000010,
        },
        {       /* 45~74.5M */
-               0x3003707f,     0x00400080,     0x02218000,     0x00000010,
+               0x3003707f,     0x00000080,     0x02218000,     0x00000010,
        },
        {       /* 77~155M */
                0x3003707f,     0x00000080,     0x02218000,     0x00000010,
@@ -3367,13 +3375,13 @@ static const uint32_t phy_misci[][4] = {
 static const uint32_t phy_dcha[][3] = {
                /*  0xe2                0xe3            0xe4 */
        {       /* 24~45M */
-               0x00000180,     0x2400c202,     0x030088a2,
+               0x00000280,     0x4400c202,     0x030088a2,
        },
        {       /* 45~74.5M */
-               0x00000180, 0x2400c202, 0x030088a2,
+               0x00000280, 0x4400c202, 0x030088a2,
        },
        {       /* 77~155M */
-               0x000002a2,     0x4800c202, 0x01009126,
+               0x000002a2,     0x6800c202, 0x01009126,
        },
        {       /* 155~340M */
                0x000002a2,     0x0800c202, 0x0100cc31,
@@ -3386,37 +3394,37 @@ static const uint32_t phy_dcha[][3] = {
        },
 };
 
-/* short cable */
-static const uint32_t phy_dchd_1[][3] = {
-               /*  0xe5                0xe6            0xe7 */
+static const uint32_t phy_dcha_reva[][3] = {
+               /*  0xe2                0xe3            0xe4 */
        {       /* 24~45M */
-               0x002e712a,     0x1e022220,     0x00018000,
+               0x00000280,     0x2400c202,     0x030088a2,
        },
        {       /* 45~74.5M */
-               0x002e714a, 0x1e022220, 0x00018000,
+               0x00000280, 0x2400c202, 0x030088a2,
        },
        {       /* 77~155M */
-               0x002c715a,     0x1e022220, 0x00018000,
+               0x000002a2,     0x4800c202, 0x01009126,
        },
        {       /* 155~340M */
-               0x002c715a,     0x1e022220, 0x00018000,
+               0x000002a2,     0x0800c202, 0x0100cc31,
        },
        {       /* 340~525M */
-               0x002c715a,     0x1e012330, 0x0001a000,
+               0x000002a2,     0x0700003c, 0x1d00cc31,
        },
        {       /* 525~600M */
-               0x002c715a,     0x1e022220, 0x00018000,
+               0x000002a2,     0x0700003c, 0x1d00cc31,
        },
 };
 
+
 /* long cable */
-static const uint32_t phy_dchd_2[][3] = {
+static const uint32_t phy_dchd_1[][3] = {
                /*      0xe5            0xe6            0xe7 */
        {       /* 24~45M */
-               0x002e712a, 0x1e062620, 0x00018000,
+               0x002e714a, 0x1e051630, 0x00018000,
        },
        {       /* 45~74.5M */
-               0x002e714a, 0x1e062620, 0x00018000,
+               0x002e714a, 0x1e051630, 0x00018000,
        },
        {       /* 77~155M */
                0x002c714a, 0x1e062620, 0x00018000,
@@ -3433,10 +3441,10 @@ static const uint32_t phy_dchd_2[][3] = {
 };
 
 /* short cable */
-static const uint32_t phy_dchd_3[][3] = {
+static const uint32_t phy_dchd_2[][3] = {
                /*  0xe5                0xe6            0xe7 */
        {       /* 24~45M */
-               0x002e712a,     0x1e022220,     0x00018000,
+               0x002e714a,     0x1e022220,     0x00018000,
        },
        {       /* 45~74.5M */
                0x002e714a, 0x1e022220, 0x00018000,
@@ -3448,15 +3456,16 @@ static const uint32_t phy_dchd_3[][3] = {
                0x002c714a,     0x1e022220, 0x00018000,
        },
        {       /* 340~525M */
-               0x002c714a,     0x1e012330, 0x0001a000,
+               0x002c714a,     0x1e022220, 0x0001a000,
        },
        {       /* 525~600M */
                0x002c714a,     0x1e022220, 0x00018000,
        },
 };
 
+
 /* long cable */
-static const uint32_t phy_dchd_4[][3] = {
+static const uint32_t phy_dchd_3[][3] = {
                /*  0xe5                0xe6            0xe7 */
        {       /* 24~45M */
                0x002e712a,     0x1e062620,     0x00018000,
@@ -3478,6 +3487,91 @@ static const uint32_t phy_dchd_4[][3] = {
        },
 };
 
+/* short cable */
+static const uint32_t phy_dchd_4[][3] = {
+               /*  0xe5                0xe6            0xe7 */
+       {       /* 24~45M */
+               0x002e712a,     0x1e022220,     0x00018000,
+       },
+       {       /* 45~74.5M */
+               0x002e714a, 0x1e022220, 0x00018000,
+       },
+       {       /* 77~155M */
+               0x002c715a,     0x1e022220, 0x00018000,
+       },
+       {       /* 155~340M */
+               0x002c715a,     0x1e022220, 0x00018000,
+       },
+       {       /* 340~525M */
+               0x002c715a,     0x1e012330, 0x0001a000,
+       },
+       {       /* 525~600M */
+               0x002c715a,     0x1e022220, 0x00018000,
+       },
+};
+
+void aml_phy_init_1(void)
+{
+       uint32_t idx = rx.phy.phy_bw;
+       uint32_t data32;
+
+       data32 = phy_misci[idx][1];
+       wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, data32);
+
+       wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2,
+               phy_misci[idx][2]);
+
+       /* reset and select data port */
+       data32 = phy_misci[idx][3];
+       data32 |= ((1 << rx.port) << 6);
+       wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
+
+       /* release reset */
+       data32 |= (1 << 11);
+       wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
+
+       udelay(5);
+       if (is_tl1_former()) {
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
+                       phy_dcha_reva[idx][0]);
+
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
+                       phy_dcha_reva[idx][1]);
+
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
+                       phy_dcha_reva[idx][2]);
+       } else {
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
+                       phy_dcha[idx][0]);
+
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
+                       phy_dcha[idx][1]);
+
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
+                       phy_dcha[idx][2]);
+       }
+       wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0,
+               phy_dchd_1[idx][0]);
+       wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2,
+               phy_dchd_1[idx][2]);
+       if ((rx.phy.cablesel % 2) == 0)
+               data32 = phy_dchd_1[idx][1];
+       else if ((rx.phy.cablesel % 2) == 1)
+               data32 = phy_dchd_2[idx][1];
+
+       wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);/*398*/
+       udelay(5);
+       data32 |= 0x00400000;
+       wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);/*398*/
+       data32 = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
+       data32 &= ~(0xf << 7);
+       wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
+       udelay(5);
+       /* data channel release reset */
+       data32 |= (0xf << 7);
+       wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
+}
+
 void aml_phy_init(void)
 {
        uint32_t idx = rx.phy.phy_bw;
@@ -3493,6 +3587,7 @@ void aml_phy_init(void)
        udelay(2);
        /* data channel and common block reset */
        data32 |= 0xf << 7;
+       udelay(5);
        wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
        udelay(2);
 
@@ -3511,15 +3606,32 @@ void aml_phy_init(void)
        wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
 
        udelay(5);
-       wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, phy_dcha[idx][0]);
+       if (is_tl1_former()) {
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
+                       phy_dcha_reva[idx][0]);
+
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
+                       phy_dcha_reva[idx][1]);
+
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
+                       phy_dcha_reva[idx][2]);
+       } else {
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
+                       phy_dcha[idx][0]);
 
-       wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, phy_dcha[idx][1]);
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
+                       phy_dcha[idx][1]);
 
-       wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, phy_dcha[idx][2]);
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
+                       phy_dcha[idx][2]);
+       }
 
        wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, phy_dchd_1[idx][0]);
        wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, phy_dchd_1[idx][2]);
-       data32 = phy_dchd_1[idx][1];
+       if ((rx.phy.cablesel % 2) == 0)
+               data32 = phy_dchd_1[idx][1];
+       else if ((rx.phy.cablesel % 2) == 1)
+               data32 = phy_dchd_2[idx][1];
 
        wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);/*398*/
        udelay(5);
@@ -3549,7 +3661,7 @@ void aml_eq_setting(void)
 
 
        wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);
-       udelay(2);
+       udelay(5);
        data32 |= 0x00400000;
        wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);
 }
@@ -3623,6 +3735,30 @@ void rx_get_best_eq_setting(void)
        }
 }
 
+bool is_tmds_clk_stable(void)
+{
+       bool ret = true;
+       uint32_t cableclk;
+       uint32_t pixel_clk;
+
+       if (rx.phy.clk_rate)
+               cableclk = rx.phy.cable_clk * 4;
+       else
+               cableclk = rx.phy.cable_clk;
+
+       pixel_clk = meson_clk_measure(29);
+       if (abs(cableclk - pixel_clk) > 5 * MHz) {
+               if (log_level & VIDEO_LOG)
+                       rx_pr("cableclk=%d,tmdsclk=%d,pixelclk=%d\n",
+                               cableclk/MHz, rx.phy.tmds_clk/MHz,
+                               meson_clk_measure(29)/MHz);
+               ret = false;
+       } else
+               ret = true;
+
+       return ret;
+}
+
 /*
  * for tl1 phy function
  */
@@ -3630,12 +3766,12 @@ struct apll_param apll_tab[] = {
        /*od for tmds: 2/4/8/16/32*/
        /*od2 for audio: 1/2/4/8/16*/
        /* bw M, N, od, od_div, od2, od2_div */
-       {pll_frq_band_0, 160, 1, 0x5, 32, 0x3, 8},/*tmdsx4*/
-       {pll_frq_band_1, 80, 1, 0x4,    16, 0x3, 8},/*tmdsx2*/
-       {pll_frq_band_2, 40, 1, 0x3, 8, 0x3, 8},/*tmds*/
-       {pll_frq_band_3, 40, 2, 0x2, 4, 0x2, 4},/*tmds*/
-       {pll_frq_band_4, 40, 1, 0x1, 2, 0x1, 2},/*tmds*/
-       {pll_frq_null, 40, 1, 0x3, 8,   0x3, 8},
+       {pll_frq_band_0, 160, 1, 0x5, 32, 0x2, 8},/*tmdsx4*/
+       {pll_frq_band_1, 80, 1, 0x4,    16, 0x2, 8},/*tmdsx2*/
+       {pll_frq_band_2, 40, 1, 0x3, 8, 0x2, 8},/*tmds*/
+       {pll_frq_band_3, 40, 2, 0x2, 4, 0x1, 4},/*tmds*/
+       {pll_frq_band_4, 40, 1, 0x1, 2, 0x0, 2},/*tmds*/
+       {pll_frq_null, 40, 1, 0x3, 8,   0x2, 8},
 };
 
 void aml_phy_pll_setting(void)
@@ -3650,6 +3786,7 @@ void aml_phy_pll_setting(void)
        uint32_t data, data2;
        uint32_t aud_div;
        uint32_t cableclk = rx.phy.cable_clk / KHz;
+       int pll_rst_cnt = 0;
 
        od_div = apll_tab[bw].od_div;
        od = apll_tab[bw].od;
@@ -3667,42 +3804,62 @@ void aml_phy_pll_setting(void)
        /*tmds clk out*/
        apll_out = (vco_clk/od_div)/5;
        aud_pll_out = ((vco_clk/od2_div)/5);
+       if (is_tl1_former())
+               od2 += 1;
+       do {
+               /*cntl0 M <7:0> N<14:10>*/
+               data = 0x00090400 & 0xffff8300;
+               data |= M;
+               data |= (N << 10);
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x20000000);
+               udelay(5);
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x30000000);
+               udelay(5);
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL1, 0x00000000);
+               udelay(5);
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00001118);
+               udelay(5);
+               data2 = 0x10058f30|od2;
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL3, data2);
+
+               /* verB: bit'27=1 */
+               if (is_tl1_former())
+                       data2 = 0x000100c0;
+               else
+                       data2 = 0x080100c0;
+               data2 |= (od << 24);
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2);
+               udelay(5);
+               /*apll_vctrl_mon_en*/
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2|0x00800000);
+               udelay(5);
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x34000000);
+               udelay(5);
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x14000000);
+               udelay(5);
+               /* bit'5: force lock bit'2: improve ldo voltage:pll 0.8v->0.9 */
+               wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x0000303c);
+               udelay(5);
+               /* common block release reset */
+               data = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
+               data &= ~(0xf << 7);
+               wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data);
+               udelay(5);
+               /* data channel release reset */
+               data |= (0xf << 7);
+               wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data);
 
-       /*cntl0 M <7:0> N<14:10>*/
-       data = 0x00090400 & 0xffff8300;
-       data |= M;
-       data |= (N << 10);
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x20000000);
-       udelay(2);
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x30000000);
-       udelay(50);
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL1, 0x00000000);
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00001118);
-       data2 = 0x10058f30|od2;
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL3, data2);
-
-       data2 = 0x000100c0 /*& 0xf8ffffff*/;
-       data2 |= (od << 24);
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2);
-       udelay(2);
-       /*apll_vctrl_mon_en*/
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2|0x00800000);
-       udelay(80);
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x34000000);
-       udelay(2);
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x14000000);
-       udelay(60);
-       /* bit'5: force lock bit'2: improve ldo voltage */
-       wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x0000303c);
-       /* common block release reset */
-       data = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
-       data &= ~(0x7 << 7);
-       wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data);
-       udelay(2);
-       /* data channel release reset */
-       data |= (0x7 << 7);
-       wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data);
-
+               mdelay(1);
+               if (pll_rst_cnt++ > pll_rst_max) {
+                       rx_pr("pll rst error\n");
+                       return;
+               }
+               if (log_level & VIDEO_LOG)
+                       rx_pr("pll init-cableclk=%d,pixelclk=%d,sq=%d\n",
+                       rx.phy.cable_clk/MHz,
+                               meson_clk_measure(29)/MHz,
+                               hdmirx_rd_top(TOP_MISC_STAT0) & 0x1);
+       } while ((!is_tmds_clk_stable()) && is_clk_stable());
        /*set audio pll divider*/
        aud_div = aud_pll_out/apll_out;
        if (aud_div == 1)
@@ -3747,10 +3904,10 @@ void aml_phy_pw_onoff(uint32_t onoff)
 void aml_phy_bw_switch(void)
 {
        aml_phy_init();
-       udelay(1);
+       udelay(10);
        aml_phy_pll_setting();
-       udelay(1);
-       aml_eq_setting();
+       udelay(10);
+       aml_phy_init_1();
 }
 
 unsigned int aml_phy_pll_lock(void)
@@ -3761,27 +3918,6 @@ unsigned int aml_phy_pll_lock(void)
                return false;
 }
 
-bool is_tmds_clk_stable(void)
-{
-       bool ret = true;
-       uint32_t cableclk;
-
-       if (rx.phy.clk_rate)
-               cableclk = rx.phy.cable_clk * 4;
-       else
-               cableclk = rx.phy.cable_clk;
-
-       if (abs(cableclk - rx.phy.tmds_clk) > 5 * MHz) {
-               if (log_level & VIDEO_LOG)
-                       rx_pr("cableclk=%d,tmdsclk=%d\n",
-                               cableclk/MHz, rx.phy.tmds_clk/MHz);
-               ret = false;
-       } else
-               ret = true;
-
-       return ret;
-}
-
 bool is_tmds_valid(void)
 {
        if (force_vic)
@@ -3796,7 +3932,7 @@ bool is_tmds_valid(void)
 unsigned int aml_phy_tmds_valid(void)
 {
        unsigned int tmds_valid;
-       unsigned int tmdsclk_valid;
+       /* unsigned int tmdsclk_valid; */
        unsigned int sqofclk;
        /* unsigned int pll_lock; */
        unsigned int tmds_align;
@@ -3804,15 +3940,15 @@ unsigned int aml_phy_tmds_valid(void)
        tmds_valid = hdmirx_rd_dwc(DWC_HDMI_PLL_LCK_STS) & 0x01;
        sqofclk = hdmirx_rd_top(TOP_MISC_STAT0) & 0x1;
        /*pll_lock = rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0) & 0x80000000;*/
-       tmdsclk_valid = is_tmds_clk_stable();
+       /* tmdsclk_valid = is_tmds_clk_stable(); */
        tmds_align = hdmirx_rd_top(TOP_TMDS_ALIGN_STAT) & 0x3f000000;
-       if (tmds_valid && sqofclk && tmdsclk_valid &&
+       if (tmds_valid && sqofclk &&
                (tmds_align == 0x3f000000))
                return true;
        else {
                if (log_level & VIDEO_LOG) {
-                       rx_pr("tmds:%x,sqo:%x,tmdsclk_valid:%x,align:%x\n",
-                               tmds_valid, sqofclk, tmdsclk_valid, tmds_align);
+                       rx_pr("tmds:%x,sqo:%x,align:%x\n",
+                               tmds_valid, sqofclk, tmds_align);
                        rx_pr("cable clk0:%d\n",
                                rx_measure_clock(MEASURE_CLK_CABLE));
                        rx_pr("cable clk1:%d\n",

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
index 38e035a..7184d16 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
@@ -1105,6 +1105,7 @@ extern int ignore_sscp_charerr;
 extern int ignore_sscp_tmds;
 extern int find_best_eq;
 extern int eq_try_cnt;
+extern int pll_rst_max;
 extern void rx_get_best_eq_setting(void);
 extern int hbr_force_8ch;
 extern void wr_reg_hhi(unsigned int offset, unsigned int val);

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
index 62521a8..d97d651 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
@@ -213,7 +213,7 @@ void hdmirx_init_params(void)
 {
        if (rx.chip_id == CHIP_ID_TL1) {
                clk_unstable_max = 10;
-               esd_phy_rst_max = 200;
+               esd_phy_rst_max = 20;
                stable_check_lvl = 0x7df;
                pll_lock_max = 1;
        } else {
@@ -985,8 +985,7 @@ static bool rx_is_timing_stable(void)
                }
        }
        if (stable_check_lvl & HACTIVE_EN) {
-               if ((diff(rx.cur.hactive, rx.pre.hactive) > diff_pixel_th) ||
-                       (rx.cur.hactive == 0)) {
+               if (diff(rx.cur.hactive, rx.pre.hactive) > diff_pixel_th) {
                        ret = false;
                        if (log_level & VIDEO_LOG)
                                rx_pr("hactive(%d=>%d),",
@@ -995,8 +994,7 @@ static bool rx_is_timing_stable(void)
                }
        }
        if (stable_check_lvl & VACTIVE_EN) {
-               if ((diff(rx.cur.vactive, rx.pre.vactive) > diff_line_th)  ||
-                       (rx.cur.vactive == 0)) {
+               if (diff(rx.cur.vactive, rx.pre.vactive) > diff_line_th) {
                        ret = false;
                        if (log_level & VIDEO_LOG)
                                rx_pr("vactive(%d=>%d),",
@@ -1709,6 +1707,8 @@ int rx_set_global_variable(const char *buf, int size)
                return pr_var(find_best_eq, index);
        if (set_pr_var(tmpbuf, eq_try_cnt, value, &index, ret))
                return pr_var(eq_try_cnt, index);
+       if (set_pr_var(tmpbuf, pll_rst_max, value, &index, ret))
+               return pr_var(pll_rst_max, index);
        if (set_pr_var(tmpbuf, hdcp_enc_mode, value, &index, ret))
                return pr_var(hdcp_enc_mode, index);
        if (set_pr_var(tmpbuf, hbr_force_8ch, value, &index, ret))
@@ -1817,6 +1817,7 @@ void rx_get_global_variable(const char *buf)
        pr_var(phy_retry_times, i++);
        pr_var(find_best_eq, i++);
        pr_var(eq_try_cnt, i++);
+       pr_var(pll_rst_max, i++);
        pr_var(hdcp_enc_mode, i++);
        pr_var(hbr_force_8ch, i++);
 }
@@ -2225,7 +2226,7 @@ void rx_main_state_machine(void)
                                        hdmirx_hw_config();
                                        hdmi_rx_top_edid_update();
                                        rx.state = FSM_HPD_LOW;
-                                       vic_check_en = false;
+                                       //vic_check_en = false;
                                        break;
                                }
                                sig_unready_cnt = 0;
@@ -2584,6 +2585,7 @@ static void dump_video_status(void)
                hdmirx_rd_top(TOP_EDID_RAM_OVR2_DATA),
                        rx.port, up_phy_addr);
        dump_clk_status();
+       rx_pr("eq=%x\n", (rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1)>>4)&0xffff);
 }
 
 static void dump_audio_status(void)