gcc/
* config/arm/types.md (type): Add rotate_imm.
* config/aarch64/aarch64.md (*ror<mode>3_insn): Split out the
ROR immediate case.
(*rorsi3_insn_uxtw): Likewise.
* config/aarch64/thunderx.md (thunderx_shift): Add rotate_imm.
* config/arm/cortex-a53.md (cortex_a53_alu_shift): Add rotate_imm.
* config/arm/cortex-a57.md (cortex_a53_alu): Add rotate_imm.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228197
138bc75d-0d04-0410-961f-
82ee72b054a4
+2015-09-28 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/arm/types.md (type): Add rotate_imm.
+ * config/aarch64/aarch64.md (*ror<mode>3_insn): Split out the
+ ROR immediate case.
+ (*rorsi3_insn_uxtw): Likewise.
+ * config/aarch64/thunderx.md (thunderx_shift): Add rotate_imm.
+ * config/arm/cortex-a53.md (cortex_a53_alu_shift): Add rotate_imm.
+ * config/arm/cortex-a57.md (cortex_a53_alu): Add rotate_imm.
+
2015-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR rtl-optimization/67481
;; Rotate right
(define_insn "*ror<mode>3_insn"
- [(set (match_operand:GPI 0 "register_operand" "=r")
- (rotatert:GPI
- (match_operand:GPI 1 "register_operand" "r")
- (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>")))]
+ [(set (match_operand:GPI 0 "register_operand" "=r,r")
+ (rotatert:GPI
+ (match_operand:GPI 1 "register_operand" "r,r")
+ (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "r,Us<cmode>")))]
""
"ror\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "shift_reg")]
+ [(set_attr "type" "shift_reg, rotate_imm")]
)
;; zero_extend version of above
operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
return "ror\\t%<w>0, %<w>1, %3";
}
- [(set_attr "type" "shift_imm")]
+ [(set_attr "type" "rotate_imm")]
)
;; zero_extend version of the above
operands[3] = GEN_INT (32 - UINTVAL (operands[2]));
return "ror\\t%w0, %w1, %3";
}
- [(set_attr "type" "shift_imm")]
+ [(set_attr "type" "rotate_imm")]
)
(define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>"
(define_insn_reservation "thunderx_shift" 1
(and (eq_attr "tune" "thunderx")
- (eq_attr "type" "bfm,extend,shift_imm,shift_reg,rbit,rev"))
+ (eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
"thunderx_pipe0 | thunderx_pipe1")
alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,csel,clz,rbit,rev,alu_dsp_reg,\
- shift_imm,shift_reg,\
+ rotate_imm,shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mrs,multiple,no_insn"))
"cortex_a53_slot_any")
alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,alu_dsp_reg,\
- shift_imm,shift_reg,\
+ rotate_imm,shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
mrs,multiple,no_insn"))
; final output, thus having no impact on scheduling.
; rbit reverse bits.
; rev reverse bytes.
+; rotate_imm rotate by immediate.
; sdiv signed division.
; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an
; immediate.
nop,\
rbit,\
rev,\
+ rotate_imm,\
sdiv,\
shift_imm,\
shift_reg,\