* h8300.h (IRA_COVER_CLASSES): Define.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@140074 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ead7b5a..baa5ec5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2008-09-06  Jeff Law <law@redhat.com>
+
+       * h8300.h (IRA_COVER_CLASSES): Define.
+
 2008-09-06  Jan Hubicka  <jh@suse.cz>
 
        PR tree-optimization/14703

diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index 4edbb2f..bc45169 100644 (file)
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -354,6 +354,19 @@ enum reg_class {
 { "NO_REGS", "COUNTER_REGS", "SOURCE_REGS", "DESTINATION_REGS", \
   "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" }
 
+/* The following macro defines cover classes for Integrated Register
+   Allocator.  Cover classes is a set of non-intersected register
+   classes covering all hard registers used for register allocation
+   purpose.  Any move between two registers of a cover class should be
+   cheaper than load or store of the registers.  The macro value is
+   array of register classes with LIM_REG_CLASSES used as the end
+   marker.  */
+
+#define IRA_COVER_CLASSES \
+{                                              \
+  GENERAL_REGS, MAC_REGS, LIM_REG_CLASSES      \
+}
+
 /* Define which registers fit in which classes.
    This is an initializer for a vector of HARD_REG_SET
    of length N_REG_CLASSES.  */