riscv: dts: jh7110: starfive: Add timer node

Add the timer node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 3190bcb..413ee61 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -530,6 +530,26 @@
                        #gpio-cells = <2>;
                };
 
+               timer@13050000 {
+                       compatible = "starfive,jh7110-timer";
+                       reg = <0x0 0x13050000 0x0 0x10000>;
+                       interrupts = <69>, <70>, <71> ,<72>;
+                       clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
+                                <&syscrg JH7110_SYSCLK_TIMER0>,
+                                <&syscrg JH7110_SYSCLK_TIMER1>,
+                                <&syscrg JH7110_SYSCLK_TIMER2>,
+                                <&syscrg JH7110_SYSCLK_TIMER3>;
+                       clock-names = "apb", "ch0", "ch1",
+                                     "ch2", "ch3";
+                       resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
+                                <&syscrg JH7110_SYSRST_TIMER0>,
+                                <&syscrg JH7110_SYSRST_TIMER1>,
+                                <&syscrg JH7110_SYSRST_TIMER2>,
+                                <&syscrg JH7110_SYSRST_TIMER3>;
+                       reset-names = "apb", "ch0", "ch1",
+                                     "ch2", "ch3";
+               };
+
                wdog: watchdog@13070000 {
                        compatible = "starfive,jh7110-wdt";
                        reg = <0x0 0x13070000 0x0 0x10000>;