drm/i915: Fix the VDSC_PW2 power domain enum value

The POWER_DOMAIN_TRANSCODER() macro depends on the
POWER_DOMAIN_TRANSCODER_A/B .. DSI_A/C enum values to be consecutive,
move POWER_DOMAIN_TRANSCODER_VDSC_PW2 after these to ensure this. The
wrong order didn't cause a problem, since the DSI_A/C domains are in
always-on power wells on all relevant platforms. The same power well
ends up being enabled/disabled when the VDSC_PW2 domain is selected
incorrectly.

While at it add a code comment about enum values that need to stay
consecutive.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220222165137.1004194-2-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9ebae7a..4ca0e61 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -153,12 +153,12 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
                return "TRANSCODER_D";
        case POWER_DOMAIN_TRANSCODER_EDP:
                return "TRANSCODER_EDP";
-       case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
-               return "TRANSCODER_VDSC_PW2";
        case POWER_DOMAIN_TRANSCODER_DSI_A:
                return "TRANSCODER_DSI_A";
        case POWER_DOMAIN_TRANSCODER_DSI_C:
                return "TRANSCODER_DSI_C";
+       case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
+               return "TRANSCODER_VDSC_PW2";
        case POWER_DOMAIN_PORT_DDI_A_LANES:
                return "PORT_DDI_A_LANES";
        case POWER_DOMAIN_PORT_DDI_B_LANES:

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index f6d0e6e..f28aa4b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -14,6 +14,11 @@ struct drm_i915_private;
 struct i915_power_well;
 struct intel_encoder;
 
+/*
+ * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
+ * consecutive, so that the pipe,transcoder,port -> power domain macros
+ * work correctly.
+ */
 enum intel_display_power_domain {
        POWER_DOMAIN_DISPLAY_CORE,
        POWER_DOMAIN_PIPE_A,
@@ -29,10 +34,12 @@ enum intel_display_power_domain {
        POWER_DOMAIN_TRANSCODER_C,
        POWER_DOMAIN_TRANSCODER_D,
        POWER_DOMAIN_TRANSCODER_EDP,
-       /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
-       POWER_DOMAIN_TRANSCODER_VDSC_PW2,
        POWER_DOMAIN_TRANSCODER_DSI_A,
        POWER_DOMAIN_TRANSCODER_DSI_C,
+
+       /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
+       POWER_DOMAIN_TRANSCODER_VDSC_PW2,
+
        POWER_DOMAIN_PORT_DDI_A_LANES,
        POWER_DOMAIN_PORT_DDI_B_LANES,
        POWER_DOMAIN_PORT_DDI_C_LANES,