notifyEvent<HWInstructionEvent>(HWInstructionDispatchedEvent(IR, UsedRegs));
}
-bool DispatchStage::checkPRF(const InstRef &IR) {
+bool DispatchStage::checkPRF(const InstRef &IR) const {
SmallVector<unsigned, 4> RegDefs;
for (const std::unique_ptr<WriteState> &RegDef :
IR.getInstruction()->getDefs())
return true;
}
-bool DispatchStage::checkRCU(const InstRef &IR) {
+bool DispatchStage::checkRCU(const InstRef &IR) const {
const unsigned NumMicroOps = IR.getInstruction()->getDesc().NumMicroOps;
if (RCU.isAvailable(NumMicroOps))
return true;
return false;
}
-bool DispatchStage::checkScheduler(const InstRef &IR) {
+bool DispatchStage::checkScheduler(const InstRef &IR) const {
HWStallEvent::GenericEventType Event;
const bool Ready = SC.canBeDispatched(IR, Event);
if (!Ready)
notifyInstructionDispatched(IR, RegisterFiles);
}
-void DispatchStage::cycleStart() {
+llvm::Error DispatchStage::cycleStart() {
AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
+ return llvm::ErrorSuccess();
}
Stage::Status DispatchStage::execute(InstRef &IR) {
RegisterFile &PRF;
Scheduler &SC;
- bool checkRCU(const InstRef &IR);
- bool checkPRF(const InstRef &IR);
- bool checkScheduler(const InstRef &IR);
+ bool checkRCU(const InstRef &IR) const;
+ bool checkPRF(const InstRef &IR) const;
+ bool checkScheduler(const InstRef &IR) const;
void dispatch(InstRef IR);
void updateRAWDependencies(ReadState &RS, const llvm::MCSubtargetInfo &STI);
// The retire stage, which controls the RCU, might have items to complete but
// RetireStage::hasWorkToComplete will check for that case.
bool hasWorkToComplete() const override { return false; }
- void cycleStart() override;
+ llvm::Error cycleStart() override;
Status execute(InstRef &IR) override;
void notifyDispatchStall(const InstRef &IR, unsigned EventType);
}
// Update the scheduler's instruction queues.
-void ExecuteStage::updateSchedulerQueues() {
+Error ExecuteStage::updateSchedulerQueues() {
SmallVector<InstRef, 4> InstructionIDs;
HWS.updateIssuedSet(InstructionIDs);
for (const InstRef &IR : InstructionIDs)
HWS.updatePendingQueue(InstructionIDs);
for (const InstRef &IR : InstructionIDs)
notifyInstructionReady(IR);
+ return ErrorSuccess();
}
// Issue instructions that are waiting in the scheduler's ready queue.
-void ExecuteStage::issueReadyInstructions() {
+Error ExecuteStage::issueReadyInstructions() {
SmallVector<InstRef, 4> InstructionIDs;
InstRef IR = HWS.select();
while (IR.isValid()) {
// Select the next instruction to issue.
IR = HWS.select();
}
+
+ return ErrorSuccess();
}
// The following routine is the maintenance routine of the ExecuteStage.
// Notifications are issued to this stage's listeners when instructions are
// moved between the HWS's queues. In particular, when an instruction becomes
// ready or executed.
-void ExecuteStage::cycleStart() {
+Error ExecuteStage::cycleStart() {
reclaimSchedulerResources();
- updateSchedulerQueues();
- issueReadyInstructions();
+ if (Error S = updateSchedulerQueues())
+ return S;
+ return issueReadyInstructions();
}
// Schedule the instruction for execution on the hardware.
// The following routines are used to maintain the HWS.
void reclaimSchedulerResources();
- void updateSchedulerQueues();
- void issueReadyInstructions();
+ llvm::Error updateSchedulerQueues();
+ llvm::Error issueReadyInstructions();
ExecuteStage(const ExecuteStage &Other) = delete;
ExecuteStage &operator=(const ExecuteStage &Other) = delete;
public:
ExecuteStage(RetireControlUnit &R, Scheduler &S) : Stage(), RCU(R), HWS(S) {}
- // The ExecuteStage will always complete all of its work per call to
- // execute(), so it is never left in a 'to-be-processed' state.
+ // This stage works under the assumption that the Pipeline will eventually
+ // execute a retire stage. We don't need to check if pipelines and/or
+ // schedulers have instructions to process, because those instructions are
+ // also tracked by the retire control unit. That means,
+ // RetireControlUnit::hasWorkToComplete() is responsible for checking if there
+ // are still instructions in-flight in the out-of-order backend.
bool hasWorkToComplete() const override { return false; }
- void cycleStart() override;
+ llvm::Error cycleStart() override;
Status execute(InstRef &IR) override;
void
void FetchStage::postExecute() { SM.updateNext(); }
-void FetchStage::cycleEnd() {
+llvm::Error FetchStage::cycleEnd() {
// Find the first instruction which hasn't been retired.
const InstMap::iterator It =
llvm::find_if(Instructions, [](const InstMap::value_type &KeyValuePair) {
// Erase instructions up to the first that hasn't been retired.
if (It != Instructions.begin())
Instructions.erase(Instructions.begin(), It);
+
+ return llvm::ErrorSuccess();
}
} // namespace mca
bool hasWorkToComplete() const override;
Status execute(InstRef &IR) override;
void postExecute() override;
- void cycleEnd() override;
+ llvm::Error cycleEnd() override;
};
} // namespace mca
}
bool Pipeline::hasWorkToProcess() {
- const auto It = llvm::find_if(Stages, [](const std::unique_ptr<Stage> &S) {
+ return llvm::any_of(Stages, [](const std::unique_ptr<Stage> &S) {
return S->hasWorkToComplete();
});
- return It != Stages.end();
}
// This routine returns early if any stage returns 'false' after execute() is
}
llvm::Error Pipeline::run() {
+ assert(!Stages.empty() && "Unexpected empty pipeline found!");
+
while (hasWorkToProcess()) {
notifyCycleBegin();
if (llvm::Error Err = runCycle())
}
llvm::Error Pipeline::runCycle() {
- // Update the stages before we do any processing for this cycle.
- InstRef IR;
- for (auto &S : Stages)
- S->cycleStart();
+ // Update stages before we start processing new instructions.
+ llvm::Error Err = llvm::ErrorSuccess();
+ for (auto I = Stages.begin(), E = Stages.end(); I != E && !Err; ++I) {
+ const std::unique_ptr<Stage> &S = *I;
+ Err = S->cycleStart();
+ }
+
+ if (Err)
+ return Err;
- // Continue executing this cycle until any stage claims it cannot make
- // progress.
+ // Now fetch and execute new instructions.
+ InstRef IR;
while (true) {
preExecuteStages();
Stage::Status Val = executeStages(IR);
postExecuteStages();
}
- for (auto &S : Stages)
- S->cycleEnd();
- return llvm::ErrorSuccess();
+ // Update stages in preparation for a new cycle.
+ for (auto I = Stages.begin(), E = Stages.end(); I != E && !Err; ++I) {
+ const std::unique_ptr<Stage> &S = *I;
+ Err = S->cycleEnd();
+ }
+ return Err;
}
void Pipeline::notifyCycleBegin() {
#include "HWEventListener.h"
#include "llvm/Support/Debug.h"
-using namespace llvm;
-
#define DEBUG_TYPE "llvm-mca"
namespace mca {
-void RetireStage::cycleStart() {
+llvm::Error RetireStage::cycleStart() {
if (RCU.isEmpty())
- return;
+ return llvm::ErrorSuccess();
const unsigned MaxRetirePerCycle = RCU.getMaxRetirePerCycle();
unsigned NumRetired = 0;
notifyInstructionRetired(Current.IR);
NumRetired++;
}
+
+ return llvm::ErrorSuccess();
}
void RetireStage::notifyInstructionRetired(const InstRef &IR) {
- LLVM_DEBUG(dbgs() << "[E] Instruction Retired: #" << IR << '\n');
- SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles());
+ LLVM_DEBUG(llvm::dbgs() << "[E] Instruction Retired: #" << IR << '\n');
+ llvm::SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles());
const Instruction &Inst = *IR.getInstruction();
const InstrDesc &Desc = Inst.getDesc();
: Stage(), RCU(R), PRF(F) {}
bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
- void cycleStart() override;
+ llvm::Error cycleStart() override;
Status execute(InstRef &IR) override { return Stage::Continue; }
void notifyInstructionRetired(const InstRef &IR);
void onInstructionExecuted(unsigned TokenID);
void updateNext() { Current++; }
const SourceRef peekNext() const {
+ assert(hasNext() && "Already at end of sequence!");
unsigned Index = getCurrentInstructionIndex();
return SourceRef(Current, Sequence[Index].get());
}
namespace mca {
// Pin the vtable here in the implementation file.
-Stage::Stage() {}
+Stage::~Stage() = default;
void Stage::addListener(HWEventListener *Listener) {
Listeners.insert(Listener);
class InstRef;
class Stage {
+ std::set<HWEventListener *> Listeners;
+
Stage(const Stage &Other) = delete;
Stage &operator=(const Stage &Other) = delete;
- std::set<HWEventListener *> Listeners;
public:
/// A Stage's execute() returns Continue, Stop, or an error. Returning
const std::set<HWEventListener *> &getListeners() const { return Listeners; }
public:
- Stage();
- virtual ~Stage() = default;
+ Stage() {}
+ virtual ~Stage();
/// Called prior to preExecute to ensure that the stage has items that it
/// is to process. For example, a FetchStage might have more instructions
/// Called once at the start of each cycle. This can be used as a setup
/// phase to prepare for the executions during the cycle.
- virtual void cycleStart() {}
+ virtual llvm::Error cycleStart() { return llvm::ErrorSuccess(); }
/// Called once at the end of each cycle.
- virtual void cycleEnd() {}
+ virtual llvm::Error cycleEnd() { return llvm::ErrorSuccess(); }
/// Called prior to executing the list of stages.
/// This can be called multiple times per cycle.
void addListener(HWEventListener *Listener);
/// Notify listeners of a particular hardware event.
- template <typename EventT> void notifyEvent(const EventT &Event) {
+ template <typename EventT> void notifyEvent(const EventT &Event) const {
for (HWEventListener *Listener : Listeners)
Listener->onEvent(Event);
}
projects / platform / upstream / llvm.git / commitdiff