drm/i915: rename intel_pm_types.h -> display/intel_wm_types.h

The file was never really about pm types, and now it's even more
obvious. Move under display as intel_wm_types.h.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230215141910.433043-4-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 52614fff0d76f4703778a3884f0e9f9adc8e49f9..b870f7f47f2b6bfa5b71e82b340522a398f70cc4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -25,7 +25,7 @@
 #include "intel_global_state.h"
 #include "intel_gmbus.h"
 #include "intel_opregion.h"
-#include "intel_pm_types.h"
+#include "intel_wm_types.h"
 
 struct drm_i915_private;
 struct drm_property;

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6e94be7c3e7f6d5a72a889ef2e6c1deadbaa069f..748b0cd411fa975966cd813767054502eb54bdb9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -53,7 +53,7 @@
 #include "intel_display_limits.h"
 #include "intel_display_power.h"
 #include "intel_dpll_mgr.h"
-#include "intel_pm_types.h"
+#include "intel_wm_types.h"
 
 struct drm_printer;
 struct __intel_global_objs_state;

diff --git a/drivers/gpu/drm/i915/display/intel_wm_types.h b/drivers/gpu/drm/i915/display/intel_wm_types.h
new file mode 100644 (file)
index 0000000..bac2b6f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_wm_types.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __INTEL_WM_TYPES_H__
+#define __INTEL_WM_TYPES_H__
+
+#include <linux/types.h>
+
+#include "display/intel_display_limits.h"
+
+enum intel_ddb_partitioning {
+       INTEL_DDB_PART_1_2,
+       INTEL_DDB_PART_5_6, /* IVB+ */
+};
+
+struct ilk_wm_values {
+       u32 wm_pipe[3];
+       u32 wm_lp[3];
+       u32 wm_lp_spr[3];
+       bool enable_fbc_wm;
+       enum intel_ddb_partitioning partitioning;
+};
+
+struct g4x_pipe_wm {
+       u16 plane[I915_MAX_PLANES];
+       u16 fbc;
+};
+
+struct g4x_sr_wm {
+       u16 plane;
+       u16 cursor;
+       u16 fbc;
+};
+
+struct vlv_wm_ddl_values {
+       u8 plane[I915_MAX_PLANES];
+};
+
+struct vlv_wm_values {
+       struct g4x_pipe_wm pipe[3];
+       struct g4x_sr_wm sr;
+       struct vlv_wm_ddl_values ddl[3];
+       u8 level;
+       bool cxsr;
+};
+
+struct g4x_wm_values {
+       struct g4x_pipe_wm pipe[2];
+       struct g4x_sr_wm sr;
+       struct g4x_sr_wm hpll;
+       bool cxsr;
+       bool hpll_en;
+       bool fbc_en;
+};
+
+struct skl_ddb_entry {
+       u16 start, end; /* in number of blocks, 'end' is exclusive */
+};
+
+static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
+{
+       return entry->end - entry->start;
+}
+
+static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
+                                      const struct skl_ddb_entry *e2)
+{
+       if (e1->start == e2->start && e1->end == e2->end)
+               return true;
+
+       return false;
+}
+
+#endif /* __INTEL_WM_TYPES_H__ */

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index f03fd991b189cb18056722114167d488e21d63e9..f91a3d4ddc0756f352755b409c6d7a2a95b0025f 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -10,7 +10,7 @@
 
 #include "intel_display_limits.h"
 #include "intel_global_state.h"
-#include "intel_pm_types.h"
+#include "intel_wm_types.h"
 
 struct drm_i915_private;
 struct intel_atomic_state;

diff --git a/drivers/gpu/drm/i915/intel_pm_types.h b/drivers/gpu/drm/i915/intel_pm_types.h
deleted file mode 100644 (file)
index 9315253..0000000
--- a/drivers/gpu/drm/i915/intel_pm_types.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2021 Intel Corporation
- */
-
-#ifndef __INTEL_PM_TYPES_H__
-#define __INTEL_PM_TYPES_H__
-
-#include <linux/types.h>
-
-#include "display/intel_display_limits.h"
-
-enum intel_ddb_partitioning {
-       INTEL_DDB_PART_1_2,
-       INTEL_DDB_PART_5_6, /* IVB+ */
-};
-
-struct ilk_wm_values {
-       u32 wm_pipe[3];
-       u32 wm_lp[3];
-       u32 wm_lp_spr[3];
-       bool enable_fbc_wm;
-       enum intel_ddb_partitioning partitioning;
-};
-
-struct g4x_pipe_wm {
-       u16 plane[I915_MAX_PLANES];
-       u16 fbc;
-};
-
-struct g4x_sr_wm {
-       u16 plane;
-       u16 cursor;
-       u16 fbc;
-};
-
-struct vlv_wm_ddl_values {
-       u8 plane[I915_MAX_PLANES];
-};
-
-struct vlv_wm_values {
-       struct g4x_pipe_wm pipe[3];
-       struct g4x_sr_wm sr;
-       struct vlv_wm_ddl_values ddl[3];
-       u8 level;
-       bool cxsr;
-};
-
-struct g4x_wm_values {
-       struct g4x_pipe_wm pipe[2];
-       struct g4x_sr_wm sr;
-       struct g4x_sr_wm hpll;
-       bool cxsr;
-       bool hpll_en;
-       bool fbc_en;
-};
-
-struct skl_ddb_entry {
-       u16 start, end; /* in number of blocks, 'end' is exclusive */
-};
-
-static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
-{
-       return entry->end - entry->start;
-}
-
-static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
-                                      const struct skl_ddb_entry *e2)
-{
-       if (e1->start == e2->start && e1->end == e2->end)
-               return true;
-
-       return false;
-}
-
-#endif /* __INTEL_PM_TYPES_H__ */