drm/i915: properly set ppgtt cacheability on snb

For some reason snb has 2 fields to set ppgtt cacheability. This one
here does not exist on gen7.

This might explain why ppgtt wasn't a win on snb like on ivb - not
enough pte caching.

v2: Fixup rebase fail.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 92acc5f..aa44ff2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3669,7 +3669,10 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
        pd_offset <<= 16;
 
        if (INTEL_INFO(dev)->gen == 6) {
-               uint32_t ecochk, gab_ctl;
+               uint32_t ecochk, gab_ctl, ecobits;
+
+               ecobits = I915_READ(GAC_ECO_BITS); 
+               I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 
                gab_ctl = I915_READ(GAB_CTL);
                I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d875fb1..a9030f8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -127,6 +127,10 @@
 #define   ECOCHK_PPGTT_CACHE64B                (0x3<<3)
 #define   ECOCHK_PPGTT_CACHE4B         (0x0<<3)
 
+#define GAC_ECO_BITS                   0x14090
+#define   ECOBITS_PPGTT_CACHE64B       (3<<8)
+#define   ECOBITS_PPGTT_CACHE4B                (0<<8)
+
 #define GAB_CTL                                0x24000
 #define   GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)