BMI088_ACCEL_MODE_ODR_MASK, regval);
}
+static int bmi088_accel_set_scale(struct bmi088_accel_data *data, int val, int val2)
+{
+ unsigned int i;
+
+ for (i = 0; i < 4; i++)
+ if (val == data->chip_info->scale_table[i][0] &&
+ val2 == data->chip_info->scale_table[i][1])
+ break;
+
+ if (i == 4)
+ return -EINVAL;
+
+ return regmap_write(data->regmap, BMI088_ACCEL_REG_ACC_RANGE, i);
+}
+
static int bmi088_accel_get_temp(struct bmi088_accel_data *data, int *val)
{
int ret;
const int **vals, int *type, int *length,
long mask)
{
+ struct bmi088_accel_data *data = iio_priv(indio_dev);
switch (mask) {
+ case IIO_CHAN_INFO_SCALE:
+ *vals = (const int *)data->chip_info->scale_table;
+ *length = 8;
+ *type = IIO_VAL_INT_PLUS_MICRO;
+ return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_SAMP_FREQ:
*type = IIO_VAL_INT_PLUS_MICRO;
*vals = bmi088_sample_freqs;
int ret;
switch (mask) {
+ case IIO_CHAN_INFO_SCALE:
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ return ret;
+
+ ret = bmi088_accel_set_scale(data, val, val2);
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+ return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
ret = pm_runtime_resume_and_get(dev);
if (ret)
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
- .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+ .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
+ BIT(IIO_CHAN_INFO_SCALE), \
.scan_index = AXIS_##_axis, \
}