x86: quark: Add platform ASL files
authorBin Meng <bmeng.cn@gmail.com>
Thu, 26 May 2016 02:19:10 +0000 (19:19 -0700)
committerBin Meng <bmeng.cn@gmail.com>
Mon, 30 May 2016 02:21:12 +0000 (10:21 +0800)
This adds basic quark platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch/x86/include/asm/arch-quark/acpi/irqroute.h [new file with mode: 0644]
arch/x86/include/asm/arch-quark/acpi/lpc.asl [new file with mode: 0644]
arch/x86/include/asm/arch-quark/acpi/platform.asl [new file with mode: 0644]
arch/x86/include/asm/arch-quark/acpi/sleepstates.asl [new file with mode: 0644]
arch/x86/include/asm/arch-quark/acpi/southcluster.asl [new file with mode: 0644]
arch/x86/include/asm/arch-quark/iomap.h [new file with mode: 0644]
arch/x86/include/asm/arch-quark/irq.h [new file with mode: 0644]

diff --git a/arch/x86/include/asm/arch-quark/acpi/irqroute.h b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
new file mode 100644 (file)
index 0000000..5ba31da
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+       PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
+       PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
+       PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+       PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
diff --git a/arch/x86/include/asm/arch-quark/acpi/lpc.asl b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
new file mode 100644 (file)
index 0000000..c3b0b1d
--- /dev/null
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+       Name(_ADR, 0x001f0000)
+
+       OperationRegion(PRTX, PCI_Config, 0x60, 8)
+       Field(PRTX, AnyAcc, NoLock, Preserve) {
+               PRTA, 8,
+               PRTB, 8,
+               PRTC, 8,
+               PRTD, 8,
+               PRTE, 8,
+               PRTF, 8,
+               PRTG, 8,
+               PRTH, 8,
+       }
+
+       #include <asm/acpi/irqlinks.asl>
+
+       /* Firmware Hub */
+       Device (FWH)
+       {
+               Name(_HID, EISAID("INT0800"))
+               Name(_CRS, ResourceTemplate()
+               {
+                       Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+               })
+       }
+
+       /* 8259 Interrupt Controller */
+       Device (PIC)
+       {
+               Name(_HID, EISAID("PNP0000"))
+               Name(_CRS, ResourceTemplate()
+               {
+                       IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+                       IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+                       IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+                       IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+                       IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+                       IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+                       IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+                       IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+                       IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+                       IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+                       IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+                       IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+                       IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+                       IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+                       IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+                       IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+                       IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+                       IRQNoFlags () { 2 }
+               })
+       }
+
+       /* 8254 timer */
+       Device (TIMR)
+       {
+               Name(_HID, EISAID("PNP0100"))
+               Name(_CRS, ResourceTemplate()
+               {
+                       IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+                       IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+                       IRQNoFlags() { 0 }
+               })
+       }
+
+       /* HPET */
+       Device (HPET)
+       {
+               Name(_HID, EISAID("PNP0103"))
+               Name(_CID, 0x010CD041)
+               Name(_CRS, ResourceTemplate()
+               {
+                       Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+               })
+
+               Method(_STA)
+               {
+                       Return (STA_VISIBLE)
+               }
+       }
+
+       /* Real Time Clock */
+       Device (RTC)
+       {
+               Name(_HID, EISAID("PNP0B00"))
+               Name(_CRS, ResourceTemplate()
+               {
+                       IO(Decode16, 0x70, 0x70, 1, 8)
+                       IRQNoFlags() { 8 }
+               })
+       }
+
+       /* LPC device: Resource consumption */
+       Device (LDRC)
+       {
+               Name(_HID, EISAID("PNP0C02"))
+               Name(_UID, 2)
+
+               Name(RBUF, ResourceTemplate()
+               {
+                       IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+                       IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+                       IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+                       IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+                       IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+                       IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+                       IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+               })
+
+               Method(_CRS, 0, NotSerialized)
+               {
+                       Return (RBUF)
+               }
+       }
+}
diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl
new file mode 100644 (file)
index 0000000..bd72842
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+       Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+       #include "southcluster.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
new file mode 100644 (file)
index 0000000..63c82fa
--- /dev/null
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-quark/acpi/southcluster.asl b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
new file mode 100644 (file)
index 0000000..a89cfaf
--- /dev/null
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+Device (PCI0)
+{
+       Name(_HID, EISAID("PNP0A08"))   /* PCIe */
+       Name(_CID, EISAID("PNP0A03"))   /* PCI */
+
+       Name(_ADR, 0)
+       Name(_BBN, 0)
+
+       Name(MCRS, ResourceTemplate()
+       {
+               /* Bus Numbers */
+               WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                               0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+               /* IO Region 0 */
+               WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                               0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+               /* PCI Config Space */
+               IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+               /* IO Region 1 */
+               WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                               0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+               /* VGA memory (0xa0000-0xbffff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+                               0x00020000, , , ASEG)
+
+               /* OPROM reserved (0xc0000-0xc3fff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+                               0x00004000, , , OPR0)
+
+               /* OPROM reserved (0xc4000-0xc7fff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+                               0x00004000, , , OPR1)
+
+               /* OPROM reserved (0xc8000-0xcbfff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+                               0x00004000, , , OPR2)
+
+               /* OPROM reserved (0xcc000-0xcffff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+                               0x00004000, , , OPR3)
+
+               /* OPROM reserved (0xd0000-0xd3fff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+                               0x00004000, , , OPR4)
+
+               /* OPROM reserved (0xd4000-0xd7fff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+                               0x00004000, , , OPR5)
+
+               /* OPROM reserved (0xd8000-0xdbfff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+                               0x00004000, , , OPR6)
+
+               /* OPROM reserved (0xdc000-0xdffff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+                               0x00004000, , , OPR7)
+
+               /* BIOS Extension (0xe0000-0xe3fff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+                               0x00004000, , , ESG0)
+
+               /* BIOS Extension (0xe4000-0xe7fff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+                               0x00004000, , , ESG1)
+
+               /* BIOS Extension (0xe8000-0xebfff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+                               0x00004000, , , ESG2)
+
+               /* BIOS Extension (0xec000-0xeffff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+                               0x00004000, , , ESG3)
+
+               /* System BIOS (0xf0000-0xfffff) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+                               0x00010000, , , FSEG)
+
+               /* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+               DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                               Cacheable, ReadWrite,
+                               0x00000000, 0x00000000, 0x00000000, 0x00000000,
+                               0x00000000, , , PMEM)
+       })
+
+       Method(_CRS, 0, Serialized)
+       {
+               /* Update PCI resource area */
+               CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+               CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+               CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+               /*
+                * Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h)
+                *
+                * TODO: for generic usage, read TOLM value from register, or
+                * from global NVS (not implemented by U-Boot yet).
+                */
+               Store(0x80000000, PMIN)
+               Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+               Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+               Return (MCRS)
+       }
+
+       /* Device Resource Consumption */
+       Device (PDRC)
+       {
+               Name(_HID, EISAID("PNP0C02"))
+               Name(_UID, 1)
+
+               Name(PDRS, ResourceTemplate() {
+                       Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000)
+                       Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+                       Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+                       IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE)
+                       IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
+                       IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE)
+               })
+
+               /* Current Resource Settings */
+               Method(_CRS, 0, Serialized)
+               {
+                       Return (PDRS)
+               }
+       }
+
+       Method(_OSC, 4)
+       {
+               /* Check for proper GUID */
+               If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+                       /* Let OS control everything */
+                       Return (Arg3)
+               } Else {
+                       /* Unrecognized UUID */
+                       CreateDWordField(Arg3, 0, CDW1)
+                       Or(CDW1, 4, CDW1)
+                       Return (Arg3)
+               }
+       }
+
+       /* LPC Bridge 0:1f.0 */
+       #include "lpc.asl"
+
+       /* IRQ routing for each PCI device */
+       #include <asm/acpi/irqroute.asl>
+}
diff --git a/arch/x86/include/asm/arch-quark/iomap.h b/arch/x86/include/asm/arch-quark/iomap.h
new file mode 100644 (file)
index 0000000..fd1ef98
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* ESRAM */
+#define ESRAM_BASE_ADDRESS             CONFIG_ESRAM_BASE
+#define ESRAM_BASE_SIZE                        ESRAM_SIZE
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS              CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE                 0x10000000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS              0xfed00000
+#define HPET_BASE_SIZE                 0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS              CONFIG_RCBA_BASE
+#define RCBA_BASE_SIZE                 0x4000
+
+/* IO Port bases */
+#define ACPI_PM1_BASE_ADDRESS          CONFIG_ACPI_PM1_BASE
+#define ACPI_PM1_BASE_SIZE             0x10
+
+#define ACPI_PBLK_BASE_ADDRESS         CONFIG_ACPI_PBLK_BASE
+#define ACPI_PBLK_BASE_SIZE            0x10
+
+#define SPI_DMA_BASE_ADDRESS           CONFIG_SPI_DMA_BASE
+#define SPI_DMA_BASE_SIZE              0x10
+
+#define GPIO_BASE_ADDRESS              CONFIG_GPIO_BASE
+#define GPIO_BASE_SIZE                 0x80
+
+#define ACPI_GPE0_BASE_ADDRESS         CONFIG_ACPI_GPE0_BASE
+#define ACPI_GPE0_BASE_SIZE            0x40
+
+#define WDT_BASE_ADDRESS               CONFIG_WDT_BASE
+#define WDT_BASE_SIZE                  0x40
+
+#endif /* _QUARK_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-quark/irq.h b/arch/x86/include/asm/arch-quark/irq.h
new file mode 100644 (file)
index 0000000..21e6830
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _QUARK_IRQ_H_
+#define _QUARK_IRQ_H_
+
+#define PIRQA_APIC_IRQ 16
+#define PIRQB_APIC_IRQ 17
+#define PIRQC_APIC_IRQ 18
+#define PIRQD_APIC_IRQ 19
+#define PIRQE_APIC_IRQ 20
+#define PIRQF_APIC_IRQ 21
+#define PIRQG_APIC_IRQ 22
+#define PIRQH_APIC_IRQ 23
+
+#endif /* _QUARK_IRQ_H_ */