+2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
+
+ * testsuite/binutils-all/objcopy.exp: Disable tic4x from test
+ * testsuite/binutils-all/objdump.exp: Setup proper values for tic4x
+ testcase
+
2002-11-14 Nick Clifton <nickc@redhat.com>
* readelf.c (process_program_headers): Add comment about return
setup_xfail "m8*-*"
setup_xfail "or32-*-rtems*" "or32-*-coff"
setup_xfail "sh-*-coff*" "sh-*-rtems*"
- setup_xfail "tic80-*-*" "w65-*" "z8*-*"
+ setup_xfail "tic4x-*-*" "tic80-*-*" "w65-*" "z8*-*"
clear_xfail "hppa*64*-*-hpux*" "hppa*-*-linux*" "hppa*-*-lites*"
clear_xfail "hppa*-*-*n*bsd*" "hppa*-*-rtems*" "*-*-*elf*" "m68*-*-sysv4*"
verbose "data name is $data_name size is $data_size"
set ets 8
set eds 4
+ # The [ti]c4x target has the property sizeof(char)=sizeof(long)=1
+ if [istarget *c4x*-*-*] then {
+ set ets 2
+ set eds 1
+ }
# c54x section sizes are in bytes, not octets; adjust accordingly
if [istarget *c54x*-*-*] then {
set ets 4
+2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
+
+ * testsuite/gas/all/gas.exp: Setup for tic4x testcase
+ * testsuite/gas/macros/macros.exp: Ditto
+ * testsuite/gas/tic4x: New tic4x gas testsuite directory
+ * testsuite/gas/tic4x/addressing.s: Create
+ * testsuite/gas/tic4x/addressing_c3x.d: Create
+ * testsuite/gas/tic4x/addressing_c4x.d: Create
+ * testsuite/gas/tic4x/allopcodes.S: Create
+ * testsuite/gas/tic4x/data.d: Create
+ * testsuite/gas/tic4x/data.s: Create
+ * testsuite/gas/tic4x/float.d: Create
+ * testsuite/gas/tic4x/float.s: Create
+ * testsuite/gas/tic4x/opclasses.h: Create
+ * testsuite/gas/tic4x/opcodes.s: Create
+ * testsuite/gas/tic4x/opcodes_c3x.d: Create
+ * testsuite/gas/tic4x/opcodes_c4x.d: Create
+ * testsuite/gas/tic4x/rebuild.sh: Create
+ * testsuite/gas/tic4x/registers.s: Create
+ * testsuite/gas/tic4x/registers_c3x.d: Create
+ * testsuite/gas/tic4x/registers_c4x.d: Create
+ * testsuite/gas/tic4x/tic4x.exp: Create
+ * testsuite/gas/tic4x/zeros.d: Create
+ * testsuite/gas/tic4x/zeros.s: Create
+
2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com>
* config/tc-tic4x.c: Remove c4x_pseudo_ignore function.
# C54x assembler (for compatibility) does not allow differences between
# forward references
# C30 counts a four byte offset as a difference of one.
-if { ![istarget hppa*-*-*]
- && ![istarget *c30*-*-*] && ![istarget *c54x*-*-*] } then {
+if { ![istarget hppa*-*-*] &&
+ ![istarget *c30*-*-*] &&
+ ![istarget *c4x*-*-*] &&
+ ![istarget *c54x*-*-*] } then {
# the vax fails because VMS can apparently actually handle this
# case in relocs, so gas doesn't handle it itself.
setup_xfail "h8300*-*-elf*" "mn10200*-*-*" "mn10300*-*-*" "vax*-*-vms*"
# These directives are done in the c54x-specific tests instead
case $target_triplet in {
{ hppa*-*-* } { }
+ { *c4x*-*-* } { }
{ *c54x*-*-* } { }
default {
run_dump_test struct
# We omit the ARM toolchains because they define locals to
# start with '.', which eliminates .eos, .text etc from the output.
# Omit c54x, since .tag and .def mean something different on that target
-if { ([istarget *-*-coff*] && ![istarget m88*-*-*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c54x*-*-coff]) \
+if { ([istarget *-*-coff*] && ![istarget m88*-*-*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c4x*-*-coff] && ![istarget *c54x*-*-coff]) \
||([istarget *-*-pe*] && ![istarget arm*-*-pe*] && ![istarget thumb*-*-pe*]) \
|| [istarget a29k-*-udi*] \
|| [istarget a29k-*-ebmon*] \
# again, p2align doesn't work on c54x target
case $target_triplet in {
{ hppa*-*-* } { }
+ { *c4x*-*-* } { }
{ *c54x*-*-* } { }
default {
test_cond
run_dump_test test1
}
-if ![istarget *c54x*-*-*] {
+if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] } {
run_dump_test test2
}
run_dump_test test3
-if ![istarget *c54x*-*-*] {
+if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] } {
run_dump_test irp
run_dump_test rept
}
case $target_triplet in {
{ hppa*-*-* } { if [istarget *-*-linux*] { run_dump_test semi } }
+ { *c4x*-*-* } { }
{ *c54x*-*-* } { }
default {
run_dump_test semi
}
}
-if { ![istarget hppa*-*-*] || [istarget *-*-linux*]} {
+if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } {
# FIXME: Due to macro mishandling of ONLY_STANDARD_ESCAPES.
setup_xfail "avr-*" "cris-*"
setup_xfail "rs6000-*-*"
# FIXME: Due to difference in what "consecutive octets" means.
- setup_xfail "*c54x*-*"
+ setup_xfail "*c4x*-*-*" "*c54x*-*"
run_dump_test strings
}
--- /dev/null
+ ;;
+ ;; test all addressing modes and register constraints
+ ;; (types/classes is read from include/opcodes/tic4x.h)
+ ;;
+ .text
+start:
+
+ ;;
+ ;; Type B - infix condition branch
+ ;;
+Type_BI:bu Type_BI ; Unconditional branch (00000)
+ bc Type_BI ; Carry branch (00001)
+ blo Type_BI ; Lower than branch (00001)
+ bls Type_BI ; Lower than or same branch (00010)
+ bhi Type_BI ; Higher than branch (00011)
+ bhs Type_BI ; Higher than or same branch (00100)
+ bnc Type_BI ; No carry branch (00100)
+ beq Type_BI ; Equal to branch (00101)
+ bz Type_BI ; Zero branch (00101)
+ bne Type_BI ; Not equal to branch (00110)
+ bnz Type_BI ; Not zero branch (00110)
+ blt Type_BI ; Less than branch (00111)
+ bn Type_BI ; Negative branch (00111)
+ ble Type_BI ; Less than or equal to branch (01000)
+ bgt Type_BI ; Greater than branch (01001)
+ bp Type_BI ; Positive branch (01001)
+ bge Type_BI ; Greater than or equal branch (01010)
+ bnn Type_BI ; Nonnegative branch (01010)
+ bnv Type_BI ; No overflow branch (01000)
+ bv Type_BI ; Overflow branch (01101)
+ bnuf Type_BI ; No underflow branch (01110)
+ buf Type_BI ; Underflow branch (01111)
+ bnlv Type_BI ; No latched overflow branch (10000)
+ blv Type_BI ; Latched overflow branch (10001)
+ bnluf Type_BI ; No latched FP underflow branch (10010)
+ bluf Type_BI ; Latched FP underflow branch (10011)
+ bzuf Type_BI ; Zero or FP underflow branch (10100)
+ b Type_BI ; Unconditional branch (00000)
+
+ ;;
+ ;; Type C - infix condition load
+ ;;
+Type_CI:ldiu R0,R0 ; Unconditional load (00000)
+ ldic R0,R0 ; Carry load (00001)
+ ldilo R0,R0 ; Lower than load (00001)
+ ldils R0,R0 ; Lower than or same load (00010)
+ ldihi R0,R0 ; Higher than load (00011)
+ ldihs R0,R0 ; Higher than or same load (00100)
+ ldinc R0,R0 ; No carry load (00100)
+ ldieq R0,R0 ; Equal to load (00101)
+ ldiz R0,R0 ; Zero load (00101)
+ ldine R0,R0 ; Not equal to load (00110)
+ ldinz R0,R0 ; Not zero load (00110)
+ ldil R0,R0 ; Less than load (00111)
+ ldin R0,R0 ; Negative load (00111)
+ ldile R0,R0 ; Less than or equal to load (01000)
+ ldigt R0,R0 ; Greater than load (01001)
+ ldip R0,R0 ; Positive load (01001)
+ ldige R0,R0 ; Greater than or equal load (01010)
+ ldinn R0,R0 ; Nonnegative load (01010)
+ ldinv R0,R0 ; No overflow load (01000)
+ ldiv R0,R0 ; Overflow load (01101)
+ ldinuf R0,R0 ; No underflow load (01110)
+ ldiuf R0,R0 ; Underflow load (01111)
+ ldinlv R0,R0 ; No latched overflow load (10000)
+ ldilv R0,R0 ; Latched overflow load (10001)
+ ldinluf R0,R0 ; No latched FP underflow load (10010)
+ ldiluf R0,R0 ; Latched FP underflow load (10011)
+ ldizuf R0,R0 ; Zero or FP underflow load (10100)
+
+ ;;
+ ;; Type * - Indirect (full)
+ ;;
+Type_ind:
+ ldi *AR0,R0 ; Indirect addressing (G=10)
+ ldi *+AR0(5),R0 ; with predisplacement add
+ ldi *-AR0(5),R0 ; with predisplacement subtract
+ ldi *++AR0(5),R0 ; with predisplacement add and modify
+ ldi *--AR0(5),R0 ; with predisplacement subtract and modify
+ ldi *AR0++(5),R0 ; with postdisplacement add and modify
+ ldi *AR0--(5),R0 ; with postdisplacement subtract and modify
+ ldi *AR0++(5)%,R0 ; with postdisplacement add and circular modify
+ ldi *AR0--(5)%,R0 ; with postdisplacement subtract and circular modify
+ ldi *+AR0(IR0),R0 ; with predisplacement add
+ ldi *-AR0(IR0),R0 ; with predisplacement subtract
+ ldi *++AR0(IR0),R0 ; with predisplacement add and modify
+ ldi *--AR0(IR0),R0 ; with predisplacement subtract and modify
+ ldi *AR0++(IR0),R0 ; with postdisplacement add and modify
+ ldi *AR0--(IR0),R0 ; with postdisplacement subtract and modify
+ ldi *AR0++(IR0)%,R0 ; with postdisplacement add and circular modify
+ ldi *AR0--(IR0)%,R0 ; with postdisplacement subtract and circular modify
+ ldi *AR0++(IR0)B,R0 ; with postincrement add and bit-reversed modify
+ ldi *AR0++,R0 ; Same as *AR0++(1)
+
+ ;;
+ ;; Type # - Direct for ldp
+ ;;
+Type_ldp:
+ ldp 12
+ ldp @start
+ ldp start
+
+ ;;
+ ;; Type @ - Direct
+ ;;
+Type_dir:
+ ldi @start,R0
+ ldi start,R0
+ ldi @16,R0
+ ldi @65535,R0
+
+ ;;
+ ;; Type A - Address register
+ ;;
+Type_A: dbc AR0,R0
+ dbc AR2,R0
+ dbc AR7,R0
+
+ ;;
+ ;; Type B - Unsigned integer (PC)
+ ;;
+Type_B: br start
+ br 0x809800
+
+ ;;
+ ;; Type C - Indirect
+ ;;
+ .ifdef TEST_C4X
+Type_C: addc3 *+AR0(5),R0,R0
+ .endif
+
+ ;;
+ ;; Type E - Register (all)
+ ;;
+Type_E: andn3 R0,R0,R0
+ andn3 AR0,R0,R0
+ addc3 DP,R0,R0
+ andn3 R7,R0,R0
+
+ ;;
+ ;; Type e - Register (0-11)
+ ;;
+Type_ee:subf3 R7,R0,R0
+ addf3 R0,R0,R0
+ addf3 R7,R0,R0
+ cmpf3 R7,R0
+ .ifdef TEST_C4X
+ addf3 R11,R0,R0
+ .endif
+
+ ;;
+ ;; Type F - Short float immediate
+ ;;
+Type_F: ldf 0,R0
+ ldf 3.5,R0
+ ldf -3.5,R0
+ ldf 0e-3.5e-1,R0
+
+ ;;
+ ;; Type G - Register (all)
+ ;;
+Type_G: andn3 R0,AR0,R0
+ addc3 R0,DP,R0
+ addc3 R0,R0,R0
+ andn3 R0,R7,R0
+
+ ;;
+ ;; Type g - Register (0-11)
+ ;;
+Type_gg:subf3 R0,R7,R0
+ addf3 R0,R0,R0
+ addf3 R0,R7,R0
+ cmpf3 R0,R7
+ .ifdef TEST_C4X
+ addf3 R0,R11,R0
+ .endif
+
+ ;;
+ ;; Type H - Register (0-7)
+ ;;
+Type_H: stf R0,*AR0 &|| stf R0,*AR0
+ stf R0,*AR0 &|| stf R2,*AR0
+ stf R0,*AR0 &|| stf R7,*AR0
+
+ ;;
+ ;; Type I - Indirect
+ ;;
+Type_I: addf3 *AR0,R0,R0 ; Indirect addressing (G=10)
+ addf3 *+AR0(1),R0,R0 ; with predisplacement add
+ addf3 *-AR0(1),R0,R0 ; with predisplacement subtract
+ addf3 *++AR0(1),R0,R0 ; with predisplacement add and modify
+ addf3 *--AR0(1),R0,R0 ; with predisplacement subtract and modify
+ addf3 *AR0++(1),R0,R0 ; with postdisplacement add and modify
+ addf3 *AR0--(1),R0,R0 ; with postdisplacement subtract and modify
+ addf3 *AR0++(1)%,R0,R0; with postdisplacement add and circular modify
+ addf3 *AR0--(1)%,R0,R0; with postdisplacement subtract and circular modify
+ addf3 *+AR0(IR0),R0,R0; with predisplacement add
+ addf3 *-AR0(IR0),R0,R0; with predisplacement subtract
+ addf3 *++AR0(IR0),R0,R0; with predisplacement add and modify
+ addf3 *--AR0(IR0),R0,R0; with predisplacement subtract and modify
+ addf3 *AR0++(IR0),R0,R0; with postdisplacement add and modify
+ addf3 *AR0--(IR0),R0,R0; with postdisplacement subtract and modify
+ addf3 *AR0++(IR0)%,R0,R0; with postdisplacement add and circular modify
+ addf3 *AR0--(IR0)%,R0,R0; with postdisplacement subtract and circular modify
+ addf3 *AR0++(IR0)B,R0,R0; with postincrement add and bit-reversed modify
+ addf3 *AR0++,R0,R0 ; Same as *AR0++(1)
+
+ ;;
+ ;; Type J - Indirect
+ ;;
+Type_J: addf3 R0,*AR0,R0 ; Indirect addressing (G=10)
+ addf3 R0,*+AR0(1),R0 ; with predisplacement add
+ addf3 R0,*-AR0(1),R0 ; with predisplacement subtract
+ addf3 R0,*++AR0(1),R0 ; with predisplacement add and modify
+ addf3 R0,*--AR0(1),R0 ; with predisplacement subtract and modify
+ addf3 R0,*AR0++(1),R0 ; with postdisplacement add and modify
+ addf3 R0,*AR0--(1),R0 ; with postdisplacement subtract and modify
+ addf3 R0,*AR0++(1)%,R0; with postdisplacement add and circular modify
+ addf3 R0,*AR0--(1)%,R0; with postdisplacement subtract and circular modify
+ addf3 R0,*+AR0(IR0),R0; with predisplacement add
+ addf3 R0,*-AR0(IR0),R0; with predisplacement subtract
+ addf3 R0,*++AR0(IR0),R0; with predisplacement add and modify
+ addf3 R0,*--AR0(IR0),R0; with predisplacement subtract and modify
+ addf3 R0,*AR0++(IR0),R0; with postdisplacement add and modify
+ addf3 R0,*AR0--(IR0),R0; with postdisplacement subtract and modify
+ addf3 R0,*AR0++(IR0)%,R0; with postdisplacement add and circular modify
+ addf3 R0,*AR0--(IR0)%,R0; with postdisplacement subtract and circular modify
+ addf3 R0,*AR0++(IR0)B,R0; with postincrement add and bit-reversed modify
+ addf3 R0,*AR0++,R0 ; Same as *AR0++(1)
+
+ ;;
+ ;; Type K - Register (0-7)
+ ;;
+Type_K: ldf *AR0,R0 &|| ldf *AR0,R0
+ ldf *AR0,R0 &|| ldf *AR0,R2
+ ldf *AR0,R0 &|| ldf *AR0,R7
+
+ ;;
+ ;; Type L - Register (0-7)
+ ;;
+Type_L: stf R0,*AR0 &|| stf R0,*AR0
+ stf R2,*AR0 &|| stf R0,*AR0
+ stf R7,*AR0 &|| stf R0,*AR0
+
+ ;;
+ ;; Type M - Register (2-3)
+ ;;
+Type_M: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
+ mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R3
+
+ ;;
+ ;; Type N - Register (0-1)
+ ;;
+Type_N: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
+ mpyf3 *AR0,*AR0,R1 &|| addf3 R0,R0,R2
+
+ ;;
+ ;; Type O - Indirect
+ ;;
+ .ifdef TEST_C4X
+Type_O: addc3 *+AR0(5),*+AR0(5),R0
+ .endif
+
+ ;;
+ ;; Type P - Displacement (PC rel)
+ ;;
+Type_P: callc start
+ callc 1
+
+ ;;
+ ;; Type Q - Register (all)
+ ;;
+Type_Q: ldi R0,R0
+ ldi AR0,R0
+ ldi DP,R0
+ ldi SP,R0
+
+ ;;
+ ;; Type q - Register (0-11)
+ ;;
+Type_qq:fix R0,R0
+ fix R7,R0
+ .ifdef TEST_C4X
+ fix R11,R0
+ absf R11,R0
+ .endif
+
+ ;;
+ ;; Type R - Register (all)
+ ;;
+Type_R: ldi R0,R0
+ ldi R0,AR0
+ ldi R0,DP
+ ldi R0,SP
+
+ ;;
+ ;; Type r - Register (0-11)
+ ;;
+Type_rr:ldf R0,R0
+ ldf R0,R7
+ .ifdef TEST_C4X
+ ldf R0,R11
+ .endif
+
+ ;;
+ ;; Type S - Signed immediate
+ ;;
+Type_S: ldi 0,R0
+ ldi -123,R0
+ ldi 6543,R0
+ ldi -32768, R0
+
+ ;;
+ ;; Type T - Integer
+ ;;
+ .ifdef TEST_C4X
+Type_T: stik 0,*AR0
+ stik 12,*AR0
+ stik -5,*AR0
+ .endif
+
+ ;;
+ ;; Type U - Unsigned integer
+ ;;
+Type_U: and 0,R0
+ and 256,R0
+ and 65535,R0
+
+ ;;
+ ;; Type V - Vector
+ ;;
+Type_V: trapu 12
+ trapu 0
+ trapu 31
+ .ifdef TEST_C4X
+ trapu 511
+ .endif
+
+ ;;
+ ;; Type W - Short int
+ ;;
+ .ifdef TEST_C4X
+Type_W: addc3 -3,R0,R0
+ addc3 5,R0,R0
+ .endif
+
+ ;;
+ ;; Type X - Expansion register
+ ;;
+ .ifdef TEST_C4X
+Type_X: ldep IVTP,R0
+ ldep TVTP,R0
+ .endif
+
+ ;;
+ ;; Type Y - Address register
+ ;;
+ .ifdef TEST_C4X
+Type_Y: lda R0,AR0
+ lda R0,DP
+ lda R0,SP
+ lda R0,IR0
+ .endif
+
+ ;;
+ ;; Type Z - Expansion register
+ ;;
+ .ifdef TEST_C4X
+Type_Z: ldpe R0,IVTP
+ ldpe R0,TVTP
+ .endif
--- /dev/null
+#as: -m30 --defsym TEST_C3X=1
+#objdump: -d -z
+#name: c3x addressing modes
+#source: addressing.s
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <Type_BI>:
+ 0: 6a00ffff.*
+ 1: 6a01fffe.*
+ 2: 6a01fffd.*
+ 3: 6a02fffc.*
+ 4: 6a03fffb.*
+ 5: 6a04fffa.*
+ 6: 6a04fff9.*
+ 7: 6a05fff8.*
+ 8: 6a05fff7.*
+ 9: 6a06fff6.*
+ a: 6a06fff5.*
+ b: 6a07fff4.*
+ c: 6a07fff3.*
+ d: 6a08fff2.*
+ e: 6a09fff1.*
+ f: 6a09fff0.*
+ 10: 6a0affef.*
+ 11: 6a0affee.*
+ 12: 6a0cffed.*
+ 13: 6a0dffec.*
+ 14: 6a0effeb.*
+ 15: 6a0fffea.*
+ 16: 6a10ffe9.*
+ 17: 6a11ffe8.*
+ 18: 6a12ffe7.*
+ 19: 6a13ffe6.*
+ 1a: 6a14ffe5.*
+ 1b: 6a00ffe4.*
+
+0000001c <Type_CI>:
+ 1c: 50000000.*
+ 1d: 50800000.*
+ 1e: 50800000.*
+ 1f: 51000000.*
+ 20: 51800000.*
+ 21: 52000000.*
+ 22: 52000000.*
+ 23: 52800000.*
+ 24: 52800000.*
+ 25: 53000000.*
+ 26: 53000000.*
+ 27: 53800000.*
+ 28: 53800000.*
+ 29: 54000000.*
+ 2a: 54800000.*
+ 2b: 54800000.*
+ 2c: 55000000.*
+ 2d: 55000000.*
+ 2e: 56000000.*
+ 2f: 56800000.*
+ 30: 57000000.*
+ 31: 57800000.*
+ 32: 58000000.*
+ 33: 58800000.*
+ 34: 59000000.*
+ 35: 59800000.*
+ 36: 5a000000.*
+
+00000037 <Type_ind>:
+ 37: 0840c000.*
+ 38: 08400005.*
+ 39: 08400805.*
+ 3a: 08401005.*
+ 3b: 08401805.*
+ 3c: 08402005.*
+ 3d: 08402805.*
+ 3e: 08403005.*
+ 3f: 08403805.*
+ 40: 08404000.*
+ 41: 08404800.*
+ 42: 08405000.*
+ 43: 08405800.*
+ 44: 08406000.*
+ 45: 08406800.*
+ 46: 08407000.*
+ 47: 08407800.*
+ 48: 0840c800.*
+ 49: 08402001.*
+
+0000004a <Type_ldp>:
+ 4a: 5070000c.*
+ 4b: 50700000.*
+ 4c: 50700000.*
+
+0000004d <Type_dir>:
+ 4d: 08200000.*
+ 4e: 08200000.*
+ 4f: 08200010.*
+ 50: 0820ffff.*
+
+00000051 <Type_A>:
+ 51: 6c010000.*
+ 52: 6c810000.*
+ 53: 6dc10000.*
+
+00000054 <Type_B>:
+ 54: 60000000.*
+ 55: 60809800.*
+
+00000056 <Type_E>:
+ 56: 22000000.*
+ 57: 22000008.*
+ 58: 20000010.*
+ 59: 22000007.*
+
+0000005a <Type_ee>:
+ 5a: 26800007.*
+ 5b: 20800000.*
+ 5c: 20800007.*
+ 5d: 23000007.*
+
+0000005e <Type_F>:
+ 5e: 07608000.*
+ 5f: 07601600.*
+ 60: 07601a00.*
+ 61: 0760eccd.*
+
+00000062 <Type_G>:
+ 62: 22000800.*
+ 63: 20001000.*
+ 64: 20000000.*
+ 65: 22000700.*
+
+00000066 <Type_gg>:
+ 66: 26800700.*
+ 67: 20800000.*
+ 68: 20800700.*
+ 69: 23000700.*
+
+0000006a <Type_H>:
+ 6a: c000c0c0.*
+ 6b: c002c0c0.*
+ 6c: c007c0c0.*
+
+0000006d <Type_I>:
+ 6d: 20c000c0.*
+ 6e: 20c00000.*
+ 6f: 20c00008.*
+ 70: 20c00010.*
+ 71: 20c00018.*
+ 72: 20c00020.*
+ 73: 20c00028.*
+ 74: 20c00030.*
+ 75: 20c00038.*
+ 76: 20c00040.*
+ 77: 20c00048.*
+ 78: 20c00050.*
+ 79: 20c00058.*
+ 7a: 20c00060.*
+ 7b: 20c00068.*
+ 7c: 20c00070.*
+ 7d: 20c00078.*
+ 7e: 20c000c8.*
+ 7f: 20c00020.*
+
+00000080 <Type_J>:
+ 80: 20a0c000.*
+ 81: 20a00000.*
+ 82: 20a00800.*
+ 83: 20a01000.*
+ 84: 20a01800.*
+ 85: 20a02000.*
+ 86: 20a02800.*
+ 87: 20a03000.*
+ 88: 20a03800.*
+ 89: 20a04000.*
+ 8a: 20a04800.*
+ 8b: 20a05000.*
+ 8c: 20a05800.*
+ 8d: 20a06000.*
+ 8e: 20a06800.*
+ 8f: 20a07000.*
+ 90: 20a07800.*
+ 91: 20a0c800.*
+ 92: 20a02000.*
+
+00000093 <Type_K>:
+ 93: c400c0c0.*
+ 94: c410c0c0.*
+ 95: c438c0c0.*
+
+00000096 <Type_L>:
+ 96: c000c0c0.*
+ 97: c080c0c0.*
+ 98: c1c0c0c0.*
+
+00000099 <Type_M>:
+ 99: 8000c0c0.*
+ 9a: 8040c0c0.*
+
+0000009b <Type_N>:
+ 9b: 8000c0c0.*
+ 9c: 8080c0c0.*
+
+0000009d <Type_P>:
+ 9d: 7201ff62.*
+ 9e: 72010001.*
+
+0000009f <Type_Q>:
+ 9f: 08000000.*
+ a0: 08000008.*
+ a1: 08000010.*
+ a2: 08000014.*
+
+000000a3 <Type_qq>:
+ a3: 05000000.*
+ a4: 05000007.*
+
+000000a5 <Type_R>:
+ a5: 08000000.*
+ a6: 08080000.*
+ a7: 08100000.*
+ a8: 08140000.*
+
+000000a9 <Type_rr>:
+ a9: 07000000.*
+ aa: 07070000.*
+
+000000ab <Type_S>:
+ ab: 08600000.*
+ ac: 0860ff85.*
+ ad: 0860198f.*
+ ae: 08608000.*
+
+000000af <Type_U>:
+ af: 02e00000.*
+ b0: 02e00100.*
+ b1: 02e0ffff.*
+
+000000b2 <Type_V>:
+ b2: 7400002c.*
+ b3: 74000020.*
+ b4: 7400003f.*
--- /dev/null
+#as: -m40 --defsym TEST_C4X=1
+#objdump: -d -z
+#name: c4x addressing modes
+#source: addressing.s
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <Type_BI>:
+ 0: 6a00ffff.*
+ 1: 6a01fffe.*
+ 2: 6a01fffd.*
+ 3: 6a02fffc.*
+ 4: 6a03fffb.*
+ 5: 6a04fffa.*
+ 6: 6a04fff9.*
+ 7: 6a05fff8.*
+ 8: 6a05fff7.*
+ 9: 6a06fff6.*
+ a: 6a06fff5.*
+ b: 6a07fff4.*
+ c: 6a07fff3.*
+ d: 6a08fff2.*
+ e: 6a09fff1.*
+ f: 6a09fff0.*
+ 10: 6a0affef.*
+ 11: 6a0affee.*
+ 12: 6a0cffed.*
+ 13: 6a0dffec.*
+ 14: 6a0effeb.*
+ 15: 6a0fffea.*
+ 16: 6a10ffe9.*
+ 17: 6a11ffe8.*
+ 18: 6a12ffe7.*
+ 19: 6a13ffe6.*
+ 1a: 6a14ffe5.*
+ 1b: 6a00ffe4.*
+
+0000001c <Type_CI>:
+ 1c: 50000000.*
+ 1d: 50800000.*
+ 1e: 50800000.*
+ 1f: 51000000.*
+ 20: 51800000.*
+ 21: 52000000.*
+ 22: 52000000.*
+ 23: 52800000.*
+ 24: 52800000.*
+ 25: 53000000.*
+ 26: 53000000.*
+ 27: 53800000.*
+ 28: 53800000.*
+ 29: 54000000.*
+ 2a: 54800000.*
+ 2b: 54800000.*
+ 2c: 55000000.*
+ 2d: 55000000.*
+ 2e: 56000000.*
+ 2f: 56800000.*
+ 30: 57000000.*
+ 31: 57800000.*
+ 32: 58000000.*
+ 33: 58800000.*
+ 34: 59000000.*
+ 35: 59800000.*
+ 36: 5a000000.*
+
+00000037 <Type_ind>:
+ 37: 0840c000.*
+ 38: 08400005.*
+ 39: 08400805.*
+ 3a: 08401005.*
+ 3b: 08401805.*
+ 3c: 08402005.*
+ 3d: 08402805.*
+ 3e: 08403005.*
+ 3f: 08403805.*
+ 40: 08404000.*
+ 41: 08404800.*
+ 42: 08405000.*
+ 43: 08405800.*
+ 44: 08406000.*
+ 45: 08406800.*
+ 46: 08407000.*
+ 47: 08407800.*
+ 48: 0840c800.*
+ 49: 08402001.*
+
+0000004a <Type_ldp>:
+ 4a: 5070000c.*
+ 4b: 50700000.*
+ 4c: 50700000.*
+
+0000004d <Type_dir>:
+ 4d: 08200000.*
+ 4e: 08200000.*
+ 4f: 08200010.*
+ 50: 0820ffff.*
+
+00000051 <Type_A>:
+ 51: 6c010000.*
+ 52: 6c810000.*
+ 53: 6dc10000.*
+
+00000054 <Type_B>:
+ 54: 60ffffab.*
+ 55: 60809800.*
+
+00000056 <Type_C>:
+ 56: 30200028.*
+
+00000057 <Type_E>:
+ 57: 22000000.*
+ 58: 22000008.*
+ 59: 20000010.*
+ 5a: 22000007.*
+
+0000005b <Type_ee>:
+ 5b: 26800007.*
+ 5c: 20800000.*
+ 5d: 20800007.*
+ 5e: 23000007.*
+ 5f: 2080001f.*
+
+00000060 <Type_F>:
+ 60: 07608000.*
+ 61: 07601600.*
+ 62: 07601a00.*
+ 63: 0760eccd.*
+
+00000064 <Type_G>:
+ 64: 22000800.*
+ 65: 20001000.*
+ 66: 20000000.*
+ 67: 22000700.*
+
+00000068 <Type_gg>:
+ 68: 26800700.*
+ 69: 20800000.*
+ 6a: 20800700.*
+ 6b: 23000700.*
+ 6c: 20801f00.*
+
+0000006d <Type_H>:
+ 6d: c000c0c0.*
+ 6e: c002c0c0.*
+ 6f: c007c0c0.*
+
+00000070 <Type_I>:
+ 70: 20c000c0.*
+ 71: 20c00000.*
+ 72: 20c00008.*
+ 73: 20c00010.*
+ 74: 20c00018.*
+ 75: 20c00020.*
+ 76: 20c00028.*
+ 77: 20c00030.*
+ 78: 20c00038.*
+ 79: 20c00040.*
+ 7a: 20c00048.*
+ 7b: 20c00050.*
+ 7c: 20c00058.*
+ 7d: 20c00060.*
+ 7e: 20c00068.*
+ 7f: 20c00070.*
+ 80: 20c00078.*
+ 81: 20c000c8.*
+ 82: 20c00020.*
+
+00000083 <Type_J>:
+ 83: 20a0c000.*
+ 84: 20a00000.*
+ 85: 20a00800.*
+ 86: 20a01000.*
+ 87: 20a01800.*
+ 88: 20a02000.*
+ 89: 20a02800.*
+ 8a: 20a03000.*
+ 8b: 20a03800.*
+ 8c: 20a04000.*
+ 8d: 20a04800.*
+ 8e: 20a05000.*
+ 8f: 20a05800.*
+ 90: 20a06000.*
+ 91: 20a06800.*
+ 92: 20a07000.*
+ 93: 20a07800.*
+ 94: 20a0c800.*
+ 95: 20a02000.*
+
+00000096 <Type_K>:
+ 96: c400c0c0.*
+ 97: c410c0c0.*
+ 98: c438c0c0.*
+
+00000099 <Type_L>:
+ 99: c000c0c0.*
+ 9a: c080c0c0.*
+ 9b: c1c0c0c0.*
+
+0000009c <Type_M>:
+ 9c: 8000c0c0.*
+ 9d: 8040c0c0.*
+
+0000009e <Type_N>:
+ 9e: 8000c0c0.*
+ 9f: 8080c0c0.*
+
+000000a0 <Type_O>:
+ a0: 30602828.*
+
+000000a1 <Type_P>:
+ a1: 7201ff5e.*
+ a2: 72010001.*
+
+000000a3 <Type_Q>:
+ a3: 08000000.*
+ a4: 08000008.*
+ a5: 08000010.*
+ a6: 08000014.*
+
+000000a7 <Type_qq>:
+ a7: 05000000.*
+ a8: 05000007.*
+ a9: 0500001f.*
+ aa: 0000001f.*
+
+000000ab <Type_R>:
+ ab: 08000000.*
+ ac: 08080000.*
+ ad: 08100000.*
+ ae: 08140000.*
+
+000000af <Type_rr>:
+ af: 07000000.*
+ b0: 07070000.*
+ b1: 071f0000.*
+
+000000b2 <Type_S>:
+ b2: 08600000.*
+ b3: 0860ff85.*
+ b4: 0860198f.*
+ b5: 08608000.*
+
+000000b6 <Type_T>:
+ b6: 1560c000.*
+ b7: 156cc000.*
+ b8: 157bc000.*
+
+000000b9 <Type_U>:
+ b9: 02e00000.*
+ ba: 02e00100.*
+ bb: 02e0ffff.*
+
+000000bc <Type_V>:
+ bc: 7400000c.*
+ bd: 74000000.*
+ be: 7400001f.*
+ bf: 740001ff.*
+
+000000c0 <Type_W>:
+ c0: 300000fd.*
+ c1: 30000005.*
+
+000000c2 <Type_X>:
+ c2: 76000000.*
+ c3: 76000001.*
+
+000000c4 <Type_Y>:
+ c4: 1e880000.*
+ c5: 1e900000.*
+ c6: 1e940000.*
+ c7: 1e910000.*
+
+000000c8 <Type_Z>:
+ c8: 76800000.*
+ c9: 76810000.*
--- /dev/null
+;;;
+;;; Test all opcodes and argument permuation
+;;; To make our job a lot simpler, we define a couple of
+;;; insn classes, that we use to generate the proper
+;;; test output.
+;;;
+;;; To rebuild this file you must use
+;;; ./rebuild.sh
+;;;
+#include "opclasses.h"
+
+ .text
+start: B_CLASS( absf )
+ P_CLASS( absf, stf )
+ A_CLASS( absi )
+ P_CLASS( absi, sti )
+ A_CLASS( addc )
+ TC_CLASS( addc )
+ B_CLASS( addf )
+ SC_CLASS( addf )
+ QC_CLASS( addf, stf )
+ A_CLASS( addi )
+ TC_CLASS( addi )
+ QC_CLASS( addi, sti )
+ AU_CLASS( and )
+ TC_CLASS( and )
+ QC_CLASS( and, sti )
+ AU_CLASS( andn )
+ T_CLASS( andn )
+ A_CLASS( ash )
+ T_CLASS( ash )
+ Q_CLASS( ash, sti )
+ J_CLASS( bC, b )
+ J_CLASS( bCd, bd )
+br_I: br start
+brd_I: brd start
+call_I: call start
+call_JS: callc R0
+ callc start
+ B_CLASS( cmpf )
+ S2_CLASS( cmpf )
+ A_CLASS( cmpi )
+ T2_CLASS( cmpi )
+ D_CLASS( dbC, db )
+ D_CLASS( dbCd, dbd )
+ AF_CLASS( fix )
+ P_CLASS( fix, sti )
+ BI_CLASS( float )
+ P_CLASS( float, stf )
+iack_Z: iack @start
+ iack *+AR0(1)
+idle_Z: idle
+ .ifdef TEST_IDLE2
+idle2_Z: idle2
+ .endif
+ B_CLASS( lde )
+ B_CLASS( ldf )
+ LL_CLASS( ldf )
+ P_CLASS( ldf, stf )
+ BB_CLASS( ldfC )
+ B6_CLASS( ldfi )
+ A_CLASS( ldi )
+ LL_CLASS( ldi )
+ P_CLASS( ldi, sti )
+ AB_CLASS( ldiC )
+ A6_CLASS( ldii )
+ldp_Z: ldp start
+ B_CLASS( ldm )
+ .ifdef TEST_LPWR
+lopower_Z: lopower
+ .endif
+ A_CLASS( lsh )
+ T_CLASS( lsh )
+ Q_CLASS( lsh, sti )
+ .ifdef TEST_LPWR
+maxspeed_Z: maxspeed
+ .endif
+ B_CLASS( mpyf )
+ SC_CLASS( mpyf )
+ M_CLASS( mpyf, addf )
+ QC_CLASS( mpyf, stf )
+ M_CLASS( mpyf, subf )
+ A_CLASS( mpyi )
+ TC_CLASS( mpyi )
+ M_CLASS( mpyi, addi )
+ QC_CLASS( mpyi, sti )
+ M_CLASS( mpyi, subi )
+ A_CLASS( negb )
+ B_CLASS( negf )
+ P_CLASS( negf, stf )
+ A_CLASS( negi )
+ P_CLASS( negi, sti )
+ A2_CLASS( nop )
+ B_CLASS( norm )
+ AU_CLASS( not )
+ P_CLASS( not, sti )
+ AU_CLASS( or )
+ TC_CLASS( or )
+ QC_CLASS( or, sti )
+ R_CLASS( pop )
+ RF_CLASS( popf )
+ R_CLASS( push )
+ RF_CLASS( pushf )
+reti_Z: retiC
+ reti
+rets_Z: retsC
+ rets
+ B_CLASS( rnd )
+ R_CLASS( rol )
+ R_CLASS( rolc )
+ R_CLASS( ror )
+ R_CLASS( rorc )
+rptb_I2: rptb start
+ A3_CLASS( rpts )
+sigi_Z: sigi
+ B7_CLASS( stf )
+ LS_CLASS( stf )
+ B7_CLASS( stfi )
+ A7_CLASS( sti )
+ LS_CLASS( sti )
+ A7_CLASS( stii )
+ A_CLASS( subb )
+ T_CLASS( subb )
+ A_CLASS( subc )
+ B_CLASS( subf )
+ S_CLASS( subf )
+ Q_CLASS( subf, stf )
+ A_CLASS( subi )
+ T_CLASS( subi )
+ Q_CLASS( subi, sti )
+ A_CLASS( subrb )
+ B_CLASS( subrf )
+ A_CLASS( subri )
+swi_Z: swi
+trap_Z: trapC 10
+ trap 10
+ AU_CLASS( tstb )
+ T2C_CLASS( tstb )
+ AU_CLASS( xor )
+ TC_CLASS( xor )
+ QC_CLASS( xor, sti )
+
+ .ifdef TEST_C4X
+ J_CLASS( bCaf, baf )
+ J_CLASS( bCat, bat )
+ B6_CLASS( frieee )
+ P_CLASS( frieee, stf )
+laj_I: laj start
+laj_JS: lajc R0
+ lajc start
+lat_Z: latC 10
+ A_CLASS( lb0 )
+ A_CLASS( lb1 )
+ A_CLASS( lb2 )
+ A_CLASS( lb3 )
+ AU_CLASS( lbu0 )
+ AU_CLASS( lbu1 )
+ AU_CLASS( lbu2 )
+ AU_CLASS( lbu3 )
+ AY_CLASS( lda )
+ldep_Z: ldep IVTP, AR0
+ldhi_Z: ldhi 35, R0
+ ldhi start, R0
+ldpe_Z: ldpe AR0, IVTP
+ldpk_Z: ldpk start
+ A_CLASS( lh0 )
+ A_CLASS( lh1 )
+ AU_CLASS( lhu0 )
+ AU_CLASS( lhu1 )
+ A_CLASS( lwl0 )
+ A_CLASS( lwl1 )
+ A_CLASS( lwl2 )
+ A_CLASS( lwl3 )
+ A_CLASS( lwr0 )
+ A_CLASS( lwr1 )
+ A_CLASS( lwr2 )
+ A_CLASS( lwr3 )
+ A_CLASS( mb0 )
+ A_CLASS( mb1 )
+ A_CLASS( mb2 )
+ A_CLASS( mb3 )
+ A_CLASS( mh0 )
+ A_CLASS( mh1 )
+ A_CLASS( mh2 )
+ A_CLASS( mh3 )
+ A_CLASS( mpyshi )
+ TC_CLASS( mpyshi )
+ A_CLASS( mpyuhi )
+ TC_CLASS( mpyuhi )
+ BA_CLASS( rcpf )
+retid_Z: retiCd
+ retid
+rptb2_I2: rptb AR0
+rptbd_I2: rptbd start
+ rptbd AR0
+ B_CLASS( rsqrf )
+ A6_CLASS( sigi )
+sti2_A7: sti -5, @start
+ sti -5, *+AR0(5)
+stik_Z: stik -5, @start
+ stik -5, *+AR0(5)
+ B_CLASS( toieee )
+ P_CLASS( toieee, stf )
+ .endif
+ .end
+
--- /dev/null
+#objdump: -dz
+#name: data tests
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <BYTE>:
+ 0: 0000000a.*
+ 1: 000000ff.*
+ 2: 00000061.*
+ 3: 00000062.*
+ 4: 00000063.*
+ 5: 00000061.*
+
+00000006 <HWORD>:
+ 6: 0000000a.*
+ 7: 0000ffff.*
+ 8: 00000061.*
+ 9: 00000062.*
+ a: 00000063.*
+ b: 00000061.*
+
+0000000c <INT>:
+ c: 0000000a.*
+ d: 00000000.*
+ e: ffffffff.*
+ f: 00000061.*
+ 10: 00000062.*
+ 11: 00000063.*
+ 12: 00000061.*
+
+00000013 <LONG>:
+ 13: ffffabcd.*
+ 14: 00000141.*
+
+00000015 <WORD>:
+ 15: 00000c80.*
+ 16: 00000042.*
+ 17: ffffffbf.*
+ 18: 0000f410.*
+ 19: 00000041.*
+
+0000001a <STRING>:
+ 1a: 44434241.*
+ 1b: 54535251.*
+ 1c: 73756f48.*
+ 1d: 306e6f74.*
+
+0000001e <ASCII>:
+ 1e: 73696854.*
+ 1f: 20736920.*
+ 20: 65762061.*
+ 21: 6c207972.*
+ 22: 20676e6f.*
+ 23: 74786574.*
+ 24: 69685400.*
+ 25: 73692073.*
+ 26: 6f6e6120.*
+ 27: 72656874.*
+ 28: 00000000.*
+
+00000029 <ASCIZ>:
+ 29: 73696854.*
+ 2a: 20736920.*
+ 2b: 65762061.*
+ 2c: 6c207972.*
+ 2d: 20676e6f.*
+ 2e: 74786574.*
+ 2f: 73696854.*
+ 30: 20736920.*
+ 31: 746f6e61.*
+ 32: 00726568.*
+
+00000033 <BLOCK>:
+ 33: 00000000.*
+ 34: 00000000.*
+ 35: 00000000.*
+ 36: 00000000.*
+
+00000037 <SPACE>:
+ 37: 00000000.*
+ 38: 00000000.*
+ 39: 00000000.*
+ 3a: 00000000.*
+
+0000003b <ALIGN>:
+ 3b: 08000000.*
+ 3c: 0c800000.*
+ 3d: 0c800000.*
+ 3e: 0c800000.*
+ 3f: 0c800000.*
+ 40: 08000000.*
--- /dev/null
+ .text
+BYTE: .byte 10,-1,"abc",'a'
+HWORD: .hword 10,-1,"abc",'a'
+INT: .int 10,IEEE,-1,"abc",'a'
+LONG: .long 0FFFFABCDH,'A'+100h
+WORD: .word 3200,1+'A',-'A',0F410h,'A'
+STRING: .string "ABCD", 51h, 52h, 53h, 54h, "Houston", 36+12
+ASCII: .ascii "This is a very long text","This is another"
+ASCIZ: .asciz "This is a very long text","This is another"
+BLOCK: .block 4
+SPACE: .space 4
+ALIGN: ldi r0,r0
+ .align
+ ldi r0,r0
--- /dev/null
+#objdump: -d -z
+#name: flonum constants
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <start>:
+ 0: 07608000.*
+ 1: 076012cd.*
+ 2: 07604580.*
+ 3: 0760e0a4.*
+ 4: 07604a80.*
+ 5: 0760ef5c.*
+ 6: 0760f800.*
+ 7: 07608000.*
+ 8: 07608000.*
+ 9: 0760f000.*
+ a: 0760e800.*
+ b: 076012cd.*
+ c: 0760e0a4.*
+ d: 07604a80.*
+ e: 0760ef5c.*
+
+0000000f <FLOAT>:
+ f: 80000000.*
+ 10: 00000000.*
+ 11: ff000000.*
+ 12: ff800000.*
+ 13: 53fba6af.*
+ 14: 01400000.*
+ 15: 06760000.*
+ 16: 01490fdb.*
+
+00000017 <SINGLE>:
+ 17: 80000000.*
+ 18: 00000000.*
+ 19: ff000000.*
+ 1a: ff800000.*
+ 1b: 53fba6af.*
+ 1c: 01400000.*
+ 1d: 06760000.*
+ 1e: 01490fdb.*
+
+0000001f <DOUBLE>:
+ 1f: 80000000.*
+ 20: 00000000.*
+ 21: ff000000.*
+ 22: ff800000.*
+ 23: 53fba6af.*
+ 24: 01400000.*
+ 25: 06760000.*
+ 26: 01490fdb.*
+
+00000027 <LDOUBLE>:
+ 27: 80000000.*
+ 28: 00000000.*
+ 29: 00000000.*
+ 2a: 00000000.*
+ 2b: ff000000.*
+ 2c: 00000000.*
+ 2d: ff800000.*
+ 2e: 80000000.*
+ 2f: 53fba6ae.*
+ 30: fba6ae9f.*
+ 31: 01400000.*
+ 32: 40000000.*
+ 33: 06760000.*
+ 34: 76000000.*
+ 35: 01490fda.*
+ 36: 490fdaa3.*
+
+00000037 <IEEE>:
+ 37: 00000000.*
+ 38: 3f800000.*
+ 39: 3f000000.*
+ 3a: bf800000.*
+ 3b: 00000000.*
+ 3c: e9045951.*
+ 3d: 40400000.*
+ 3e: 42f60000.*
+ 3f: 40490fdb.*
--- /dev/null
+ ;; test float numbers and constants
+ .text
+ ;; Standard GAS syntax
+start: ldf 0e0, f0
+ ldf 0e2.7, f0
+ ldf 0e2.7e1, f0
+ ldf 0e2.7e-1, f0
+ ldf 0e-2.7e1, f0
+ ldf 0e-2.7e-1, f0
+ ldf -0e1.0, f0
+
+ ;; Standard TI syntax
+ ldf 0, f0
+ ldf 0.0, f0
+ ldf 0.5, f0
+ ldf -0.5, f0
+ ldf 2.7, f0
+ ldf 2.7e-1, f0
+ ldf -2.7e1, f0
+ ldf -2.7e-1, f0
+
+FLOAT: .float 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654
+SINGLE: .single 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654
+DOUBLE: .double 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654
+LDOUBLE: .ldouble 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654
+IEEE: .ieee 0f0, 0f1.0, 0f0.5, 0f-1,0, 0e-1.0e25, 3, 123, 0f3.141592654
+
+ .end
--- /dev/null
+/* Opcode infix
+ B condition 16--20 U,C,Z,LO,HI, etc.
+ C condition 23--27 U,C,Z,LO,HI, etc.
+
+ Arguments
+ , required arg follows
+ ; optional arg follows
+
+ General addressing modes
+ * indirect 0--15 *+AR0(5), *++AR0(IR0)
+ # direct (for ldp only) 0--15 @start, start
+ @ direct 0--15 @start, start
+ F short float immediate 0--15 3.5, 0e-3.5e-1
+ Q register 0--15 R0, AR0, DP, SP
+ R register 16--20 R0, AR0, DP, SP
+ S short int immediate 0--15 -5, 5
+ D src and dst same reg
+
+ Three operand addressing modes
+ E register 0--7 R0, R7, R11
+ G register 8--15 R0, R7, R11
+ I indirect(short) 0--7 *+AR0(1), *+AR0(IR0)
+ J indirect(short) 8--15 *+AR0(1), *+AR0(IR0)
+ R register 16--20 R0, R7, R11
+ W short int (C4x) 0--7 -3, 5
+ C indirect(short) (C4x) 0--7 *+AR0(5)
+ O indirect(short) (C4x) 8--15 *+AR0(5)
+
+ Parallel instruction addressing modes
+ E register 0--7 R0, R7, R11
+ G register 8--15 R0, R7, R11
+ H register 18--16 R0, R7
+ I indirect(short) 0--7 *+AR0(1), *+AR0(IR0)
+ J indirect(short) 8--15 *+AR0(1), *+AR0(IR0)
+ K register 19--21 R0, R7
+ L register 22--24 R0, R7
+ M register (R2,R3) 22--22 R2, R3
+ N register (R0,R1) 23--23 R0, R1
+
+ Misc. addressing modes
+ A address register 22--24 AR0, AR7
+ B unsigned integer 0--23 @start, start (absolute on C3x, relative on C4x)
+ P displacement (PC Rel) 0--15 @start, start
+ U unsigned integer 0--15 0, 65535
+ V vector (C4x: 0--8) 0--4 25, 7
+ T integer (C4x) 16--20 -5, 12
+ Y address reg (C4x) 16--20 AR0, DP, SP, IR0
+ X expansion reg (C4x) 0--4 IVTP, TVTP
+ Z expansion reg (C4x) 16--20 IVTP, TVTP
+*/
+
+/* A: General 2-operand integer operations
+ Syntax: <i> src, dst
+ src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+ dst = Register (R)
+ Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,
+ SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
+ MBn, MHn, MPYSHI, MPYUHI
+*/
+#define A_CLASS(name) \
+name##_A: &\
+ name AR1, AR0 /* Q;R */ &\
+ name AR0 /* Q;R */ &\
+ name @start, AR0 /* @,R */ &\
+ name *+AR0(5), AR0 /* *,R */ &\
+ name -5, AR0 /* S,R */
+
+
+/* AB: General 2-operand integer operation with condition
+ Syntax: <i>c src, dst
+ c = Condition
+ src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+ dst = Register (R)
+ Instr: 1/0 - LDIc
+*/
+#define AB_CLASS(name) \
+name##_AB: &\
+ name AR1, AR0 /* Q;R */ &\
+ name AR0 /* Q;R */ &\
+ name @start, AR0 /* @,R */ &\
+ name *+AR0(5), AR0 /* *,R */ &\
+ name -5, AR0 /* S,R */
+
+
+/* AU: General 2-operand unsigned integer operation
+ Syntax: <i> src, dst
+ src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
+ dst = Register (R)
+ Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
+*/
+#define AU_CLASS(name) \
+name##_AU: &\
+ name AR1, AR0 /* Q;R */ &\
+ name AR0 /* Q;R */ &\
+ name @start, AR0 /* @,R */ &\
+ name *+AR0(5), AR0 /* *,R */ &\
+ name 5, AR0 /* U,R */
+
+
+/* AF: General 2-operand float to integer operation
+ Syntax: <i> src, dst
+ src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F)
+ dst = Register (R)
+ Instr: 1/0 - FIX
+*/
+#define AF_CLASS(name) \
+name##_AF: &\
+ name R1, R0 /* Q;R */ &\
+ name R0 /* Q;R */ &\
+ name @start, AR0 /* @,R */ &\
+ name *+AR0(5), AR0 /* *,R */ &\
+ name 3.5, AR0 /* F,R */
+
+
+/* A2: Limited 1-operand (integer) operation
+ Syntax: <i> src
+ src = Register (Q), Indirect (*), None
+ Instr: 1/0 - NOP
+*/
+#define A2_CLASS(name) \
+name##_A2: &\
+ name AR0 /* Q */ &\
+ name *+AR0(5) /* * */ &\
+ name /* */
+
+
+/* A3: General 1-operand unsigned integer operation
+ Syntax: <i> src
+ src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
+ Instr: 1/0 - RPTS
+*/
+#define A3_CLASS(name) \
+name##_A3: &\
+ name AR1 /* Q */ &\
+ name @start /* @ */ &\
+ name *+AR0(5) /* * */ &\
+ name 5 /* U */
+
+
+/* A6: Limited 2-operand integer operation
+ Syntax: <i> src, dst
+ src = Direct (@), Indirect (*)
+ dst = Register (R)
+ Instr: 1/1 - LDII, C4x: SIGI
+*/
+#define A6_CLASS(name) \
+name##_A6: &\
+ name @start, AR0 /* @,R */ &\
+ name *+AR0(5), AR0 /* *,R */
+
+
+/* A7: Limited 2-operand integer store operation
+ Syntax: <i> src, dst
+ src = Register (R)
+ dst = Direct (@), Indirect (*)
+ Instr: 2/0 - STI, STII
+*/
+#define A7_CLASS(name) \
+name##_A7: &\
+ name AR0, @start /* R,@ */ &\
+ name AR0, *+AR0(5) /* R,* */
+
+
+/* AY: General 2-operand signed address load operation
+ Syntax: <i> src, dst
+ src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+ dst = Address register - ARx, IRx, DP, BK, SP (Y)
+ Instr: 0/1 - C4x: LDA
+ Note: Q and Y should *never* be the same register
+*/
+#define AY_CLASS(name) \
+name##_AY: &\
+ name AR1, AR0 /* Q,Y */ &\
+ name @start, AR0 /* @,Y */ &\
+ name *+AR0(5), AR0 /* *,Y */ &\
+ name -5, AR0 /* S,Y */
+
+
+/* B: General 2-operand float operation
+ Syntax: <i> src, dst
+ src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F)
+ dst = Register 0-11 (R)
+ Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
+ SUBF, SUBRF, C4x: RSQRF, TOIEEE
+*/
+#define B_CLASS(name) \
+name##_B: &\
+ name R1, R0 /* Q;R */ &\
+ name R0 /* Q;R */ &\
+ name @start, R0 /* @,R */ &\
+ name *+AR0(5), R0 /* *,R */ &\
+ name 3.5, R0 /* F,R */
+
+
+/* BA: General 2-operand integer to float operation
+ Syntax: <i> src, dst
+ src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
+ dst = Register 0-11 (R)
+ Instr: 0/1 - C4x: CRCPF
+*/
+#define BA_CLASS(name) \
+name##_BA: &\
+ name AR1, R0 /* Q;R */ &\
+ name R0 /* Q;R */ &\
+ name @start, R0 /* @,R */ &\
+ name *+AR0(5), R0 /* *,R */ &\
+ name 3.5, R0 /* F,R */
+
+
+/* BB: General 2-operand conditional float operation
+ Syntax: <i>c src, dst
+ c = Condition
+ src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F)
+ dst = Register 0-11 (R)
+ Instr: 1/0 - LDFc
+*/
+#define BB_CLASS(name) \
+name##_BB: &\
+ name R1, R0 /* Q;R */ &\
+ name R0 /* Q;R */ &\
+ name @start, R0 /* @,R */ &\
+ name *+AR0(5), R0 /* *,R */ &\
+ name 3.5, R0 /* F,R */
+
+
+/* BI: General 2-operand integer to float operation (yet different to BA)
+ Syntax: <i> src, dst
+ src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+ dst = Register 0-11 (R)
+ Instr: 1/0 - FLOAT
+*/
+#define BI_CLASS(name) \
+name##_BI: &\
+ name AR1, R0 /* Q;R */ &\
+ name R0 /* Q;R */ &\
+ name @start, R0 /* @,R */ &\
+ name *+AR0(5), R0 /* *,R */ &\
+ name -5, R0 /* S,R */
+
+
+/* B6: Limited 2-operand float operation
+ Syntax: <i> src, dst
+ src = Direct (@), Indirect (*)
+ dst = Register 0-11 (R)
+ Instr: 1/1 - LDFI, C4x: FRIEEE
+*/
+#define B6_CLASS(name) \
+name##_B6: &\
+ name @start, R0 /* @,R */ &\
+ name *+AR0(5), R0 /* *,R */
+
+
+/* B7: Limited 2-operand float store operation
+ Syntax: <i> src, dst
+ src = Register 0-11 (R)
+ dst = Direct (@), Indirect (*)
+ Instr: 2/0 - STF, STFI
+*/
+#define B7_CLASS(name) \
+name##_B7: &\
+ name R0, @start /* R,@ */ &\
+ name R0, *+AR0(5) /* R,* */
+
+
+/* D: Decrement and brach operations
+ Syntax: <i>c ARn, dst
+ c = condition
+ ARn = AR register 0-11 (A)
+ dst = Register (Q), PC-relative (P)
+ Instr: 2/0 - DBc, DBcD
+ Alias: <name1> <name2>
+*/
+#define D_CLASS(name1, name2) \
+name1##_D: &\
+ name1 AR0, R0 /* A,Q */ &\
+ name1 AR0, start /* A,P */ &\
+name2##_D: &\
+ name2 AR0, R0 /* A,Q */ &\
+ name2 AR0, start /* A,P */
+
+
+/* J: General conditional branch operations
+ Syntax: <i>c dst
+ c = Condition
+ dst = Register (Q), PC-relative (P)
+ Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
+ Alias: <name1> <name2>
+*/
+#define J_CLASS(name1, name2) \
+name1##_J: &\
+ name1 R0 /* Q */ &\
+ name1 start /* P */ &\
+name2##_J: &\
+ name2 R0 /* Q */ &\
+ name2 start /* P */
+
+
+/* LL: Load-load parallell operation
+ Syntax: <i> src2, dst2 || <i> src1, dst1
+ src1 = Indirect 0,1,IR0,IR1 (J)
+ dst1 = Register 0-7 (K)
+ src2 = Indirect 0,1,IR0,IR1 (I)
+ dst2 = Register 0-7 (L)
+ Instr: 2/0 - LDF||LDF, LDI||LDI
+ Alias: i||i, i1||i2, i2||i1
+*/
+#define LL_CLASS(name) \
+name##_LL: &\
+ name *+AR0(1), R0 &|| name *+AR1(1), R1 /* I,L|J,K */ &\
+ name##2 *+AR0(1), R0 &|| name##1 *+AR1(1), R1 /* I,L|J,K */ &\
+ name##1 *+AR1(1), R1 &|| name##2 *+AR0(1), R0 /* J,K|I,L */
+
+
+/* LS: Store-store parallell operation
+ Syntax: <i> src2, dst2 || <i> src1, dst1
+ src1 = Register 0-7 (H)
+ dst1 = Indirect 0,1,IR0,IR1 (J)
+ src2 = Register 0-7 (L)
+ dst2 = Indirect 0,1,IR0,IR1 (I)
+ Instr: 2/0 - STF||STF, STI||STI
+ Alias: i||i, i1||i2, i2||i1.
+*/
+#define LS_CLASS(name) \
+name##_LS: &\
+ name R0, *+AR0(1) &|| name R1, *+AR1(1) /* L,I|H,J */ &\
+ name##2 R0, *+AR0(1) &|| name##1 R1, *+AR1(1) /* L,I|H,J */ &\
+ name##1 R1, *+AR1(1) &|| name##2 R0, *+AR0(1) /* H,J|L,I */
+
+
+/* M: General multiply and add/sub operations
+ Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
+ <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual
+ <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01]
+ <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual
+ <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual
+ <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
+ src1 = Register 0-7 (K)
+ src2 = Register 0-7 (H)
+ src3 = Indirect 0,1,IR0,IR1 (J)
+ src4 = Indirect 0,1,IR0,IR1 (I)
+ dst1 = Register 0-1 (N)
+ dst2 = Register 2-3 (M)
+ Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
+ Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
+*/
+#define M_CLASS(namea, nameb) \
+namea##_##nameb##_M: &\
+ namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* I,J,N|H,K;M */ &\
+ namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* I,J,N|H,K;M */ &\
+ namea *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
+ namea *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
+ namea R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
+ namea R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
+ namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
+ namea *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
+ namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
+ namea *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K,J,N|I,H;M */ &\
+namea##3_##nameb##_M: &\
+ namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* I,J,N|H,K;M */ &\
+ namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* I,J,N|H,K;M */ &\
+ namea##3 *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
+ namea##3 R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
+ namea##3 R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
+ namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
+ namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K,J,N|I,H;M */ &\
+namea##_##nameb##3_M: &\
+ namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* I,J,N|H,K;M */ &\
+ namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* I,J,N|H,K;M */ &\
+ namea *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
+ namea *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
+ namea R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
+ namea R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
+ namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
+ namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
+ namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
+ namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K,J,N|I,H;M */ &\
+namea##3_##nameb##3_M: &\
+ namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* I,J,N|H,K;M */ &\
+ namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* I,J,N|H,K;M */ &\
+ namea##3 *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
+ namea##3 R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
+ namea##3 R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
+ namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
+ namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K,J,N|I,H;M */ &\
+nameb##_##namea##_M: &\
+ nameb R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
+ nameb R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H,I,M|J,K;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
+ nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* I,J,M|H,K;N */ &\
+ nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* I,J,M|H,K;N */ &\
+ nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
+ nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
+ nameb *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
+ nameb *+AR1(1), R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
+ nameb *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
+ nameb *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
+nameb##3_##namea##3_M: &\
+ nameb##3 R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
+ nameb##3 R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H,I,M|J,K;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
+ nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* I,J,M|H,K;N */ &\
+ nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* I,J,M|H,K;N */ &\
+ nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
+ nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
+ nameb##3 *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
+nameb##_##namea##3_M: &\
+ nameb R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
+ nameb R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H,I,M|J,K;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
+ nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* I,J,M|H,K;N */ &\
+ nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* I,J,M|H,K;N */ &\
+ nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
+ nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
+ nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
+ nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
+ nameb *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
+ nameb *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
+nameb##3_##namea##_M: &\
+ nameb##3 R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
+ nameb##3 R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H,I,M|J,K;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
+ nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* I,J,M|H,K;N */ &\
+ nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* I,J,M|H,K;N */ &\
+ nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
+ nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
+ nameb##3 *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
+
+
+/* P: General 2-operand operation with parallell store
+ Syntax: <ia> src2, dst1 || <ib> src3, dst2
+ src2 = Indirect 0,1,IR0,IR1 (I)
+ dst1 = Register 0-7 (L)
+ src3 = Register 0-7 (H)
+ dst2 = Indirect 0,1,IR0,IR1 (J)
+ Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF,
+ LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF,
+ TOIEEE||STF
+ Alias: a||b, b||a
+*/
+#define P_CLASS(namea, nameb) \
+namea##_##nameb##_P: &\
+ namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|I,L */
+
+
+/* Q: General 3-operand operation with parallell store
+ Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
+ src1 = Register 0-7 (K)
+ src2 = Indirect 0,1,IR0,IR1 (I)
+ dst1 = Register 0-7 (L)
+ src3 = Register 0-7 (H)
+ dst2 = Indirect 0,1,IR0,IR1 (J)
+ Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI
+ Alias: a||b, b||a, a3||b, b||a3
+*/
+#define Q_CLASS(namea, nameb) \
+namea##_##nameb##_Q: &\
+ namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K,I,L */ &\
+namea##3_##nameb##_Q: &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K,I,L */
+
+
+/* QC: General commutative 3-operand operation with parallell store
+ Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
+ <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
+ src1 = Register 0-7 (K)
+ src2 = Indirect 0,1,IR0,IR1 (I)
+ dst1 = Register 0-7 (L)
+ src3 = Register 0-7 (H)
+ dst2 = Indirect 0,1,IR0,IR1 (J)
+ Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI,
+ OR3||STI, XOR3||STI
+ Alias: a||b, b||a, a3||b, b||a3
+*/
+#define QC_CLASS(namea, nameb) \
+namea##_##nameb##_QC: &\
+ namea *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
+ namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
+ namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea *+AR0(1), R1, R0 /* H,J|I,K;L */ &\
+ nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|I,K;L */ &\
+ nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K,I,L */ &\
+namea##3_##nameb##_QC: &\
+ namea##3 *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
+ namea##3 *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R1, R0 /* H,J|I,K;L */ &\
+ nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R0 /* H,J|I,K;L */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K,I,L */
+
+
+/* R: General register integer operation
+ Syntax: <i> dst
+ dst = Register (R)
+ Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC
+*/
+#define R_CLASS(name) \
+name##_R: &\
+ name AR0 /* R */
+
+
+/* RF: General register float operation
+ Syntax: <i> dst
+ dst = Register 0-11 (R)
+ Instr: 2/0 - POPF, PUSHF
+*/
+#define RF_CLASS(name) \
+name##_RF: &\
+ name F0 /* R */
+
+
+/* S: General 3-operand float operation
+ Syntax: <i> src2, src1, dst
+ src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+ src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+ dst = Register 0-11 (R)
+ Instr: 1/0 - SUBF3
+ Alias: i, i3
+*/
+#define S_CLASS(name) \
+name##_S: &\
+ name R2, R1, R0 /* E,G;R */ &\
+ name R1, R0 /* E,G;R */ &\
+ name R1, *+AR0(1), R0 /* E,J,R */ &\
+ name *+AR0(1), R1, R0 /* I,G;R */ &\
+ name *+AR0(1), R0 /* I,G;R */ &\
+ name *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
+ .ifdef TEST_C4X &\
+ name *+AR0(5), R1, R0 /* C,G;R */ &\
+ name *+AR0(5), R0 /* C,G;R */ &\
+ name *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
+ .endif &\
+name##3_S: &\
+ name##3 R2, R1, R0 /* E,G;R */ &\
+ name##3 R1, R0 /* E,G;R */ &\
+ name##3 R1, *+AR0(1), R0 /* E,J,R */ &\
+ name##3 *+AR0(1), R1, R0 /* I,G;R */ &\
+ name##3 *+AR0(1), R0 /* I,G;R */ &\
+ name##3 *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
+ .ifdef TEST_C4X &\
+ name##3 *+AR0(5), R1, R0 /* C,G;R */ &\
+ name##3 *+AR0(5), R0 /* C,G;R */ &\
+ name##3 *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
+ .endif
+
+
+/* SC: General commutative 3-operand float operation
+ Syntax: <i> src2, src1, dst - Manual
+ <i> src1, src2, dst
+ src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+ src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+ dst = Register 0-11 (R)
+ Instr: 2/0 - ADDF3, MPYF3
+ Alias: i, i3
+*/
+#define SC_CLASS(name) \
+name##_SC: &\
+ name R2, R1, R0 /* E,G;R */ &\
+ name R1, R0 /* E,G;R */ &\
+ name R1, *+AR0(1), R0 /* E,J,R */ &\
+ name *+AR0(1), R1, R0 /* I,G;R */ &\
+ name *+AR0(1), R0 /* I,G;R */ &\
+ name *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
+ .ifdef TEST_C4X &\
+ name *+AR0(5), R1, R0 /* C,G;R */ &\
+ name *+AR0(5), R0 /* C,G;R */ &\
+ name R1, *+AR0(5), R0 /* G,C,R */ &\
+ name *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
+ .endif &\
+name##3_SC: &\
+ name##3 R2, R1, R0 /* E,G;R */ &\
+ name##3 R1, R0 /* E,G;R */ &\
+ name##3 R1, *+AR0(1), R0 /* E,J,R */ &\
+ name##3 *+AR0(1), R1, R0 /* I,G;R */ &\
+ name##3 *+AR0(1), R0 /* I,G;R */ &\
+ name##3 *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
+ .ifdef TEST_C4X &\
+ name##3 *+AR0(5), R1, R0 /* C,G;R */ &\
+ name##3 *+AR0(5), R0 /* C,G;R */ &\
+ name##3 R1, *+AR0(5), R0 /* G,C,R */ &\
+ name##3 *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
+ .endif
+
+
+/* S2: General 3-operand float operation with 2 args
+ Syntax: <i> src2, src1
+ src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+ src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+ Instr: 1/0 - CMPF3
+ Alias: i, i3
+*/
+#define S2_CLASS(name) \
+name##_S2: &\
+ name R2, R1 /* E,G */ &\
+ name R1, *+AR0(1) /* E,J */ &\
+ name *+AR0(1), R1 /* I,G */ &\
+ name *+AR0(1), *+AR1(1) /* I,J */ &\
+ .ifdef TEST_C4X &\
+ name *+AR0(5), R1 /* C,G */ &\
+ name *+AR0(5), *+AR1(5) /* C,O */ &\
+ .endif &\
+name##3_S2: &\
+ name##3 R2, R1 /* E,G */ &\
+ name##3 R1, *+AR0(1) /* E,J */ &\
+ name##3 *+AR0(1), R1 /* I,G */ &\
+ name##3 *+AR0(1), *+AR1(1) /* I,J */ &\
+ .ifdef TEST_C4X &\
+ name##3 *+AR0(5), R1 /* C,G */ &\
+ name##3 *+AR0(5), *+AR1(5) /* C,O */ &\
+ .endif
+
+
+/* T: General 3-operand integer operand
+ Syntax: <i> src2, src1, dst
+ src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+ src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+ dst = Register (R)
+ Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3
+ Alias: i, i3
+*/
+#define T_CLASS(name) \
+name##_T: &\
+ name AR2, AR1, AR0 /* E,G;R */ &\
+ name AR1, AR0 /* E,G;R */ &\
+ name AR1, *+AR0(1), AR0 /* E,J,R */ &\
+ name *+AR0(1), AR1, AR0 /* I,G;R */ &\
+ name *+AR0(1), AR0 /* I,G;R */ &\
+ name *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
+ .ifdef TEST_C4X &\
+ name 5, AR1, AR0 /* W,G;R */ &\
+ name 5, AR0 /* W,G;R */ &\
+ name *+AR0(5), AR1, AR0 /* C,G;R */ &\
+ name *+AR0(5), AR0 /* C,G;R */ &\
+ name 5, *+AR0(5), AR0 /* W,O,R */ &\
+ name *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
+ .endif &\
+name##3_T: &\
+ name##3 AR2, AR1, AR0 /* E,G;R */ &\
+ name##3 AR1, AR0 /* E,G;R */ &\
+ name##3 AR1, *+AR0(1), AR0 /* E,J,R */ &\
+ name##3 *+AR0(1), AR1, AR0 /* I,G;R */ &\
+ name##3 *+AR0(1), AR0 /* I,G;R */ &\
+ name##3 *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
+ .ifdef TEST_C4X &\
+ name##3 -5, AR1, AR0 /* W,G;R */ &\
+ name##3 -5, AR0 /* W,G;R */ &\
+ name##3 *+AR0(5), AR1, AR0 /* C,G;R */ &\
+ name##3 *+AR0(5), AR0 /* C,G;R */ &\
+ name##3 -5, *+AR0(5), AR0 /* W,O,R */ &\
+ name##3 *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
+ .endif
+
+
+/* TC: General commutative 3-operand integer operation
+ Syntax: <i> src2, src1, dst
+ <i> src1, src2, dst
+ src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+ src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+ dst = Register (R)
+ Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI
+ Alias: i, i3
+*/
+#define TC_CLASS(name) \
+name##_TC: &\
+ name AR2, AR1, AR0 /* E,G;R */ &\
+ name AR1, AR0 /* E,G;R */ &\
+ name AR1, *+AR0(1), AR0 /* E,J,R */ &\
+ name *+AR0(1), AR1, AR0 /* I,G;R */ &\
+ name *+AR0(1), AR0 /* I,G;R */ &\
+ name *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
+ .ifdef TEST_C4X &\
+ name 5, AR1, AR0 /* W,G;R */ &\
+ name 5, AR0 /* W,G;R */ &\
+ name AR1, -5, AR0 /* G,W,R */ &\
+ name *+AR0(5), AR1, AR0 /* C,G;R */ &\
+ name *+AR0(5), AR0 /* C,G;R */ &\
+ name AR1, *+AR0(5), AR0 /* G,C,R */ &\
+ name 5, *+AR0(5), AR0 /* W,O,R */ &\
+ name *+AR0(5), -5, AR0 /* O,W,R */ &\
+ name *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
+ .endif &\
+name##3_TC: &\
+ name##3 AR2, AR1, AR0 /* E,G;R */ &\
+ name##3 AR1, AR0 /* E,G;R */ &\
+ name##3 AR1, *+AR0(1), AR0 /* E,J,R */ &\
+ name##3 *+AR0(1), AR1, AR0 /* I,G;R */ &\
+ name##3 *+AR0(1), AR0 /* I,G;R */ &\
+ name##3 *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
+ .ifdef TEST_C4X &\
+ name##3 -5, AR1, AR0 /* W,G;R */ &\
+ name##3 -5, AR0 /* W,G;R */ &\
+ name##3 AR1, -5, AR0 /* G,W,R */ &\
+ name##3 *+AR0(5), AR1, AR0 /* C,G;R */ &\
+ name##3 *+AR0(5), AR0 /* C,G;R */ &\
+ name##3 AR1, *+AR0(5), AR0 /* G,C,R */ &\
+ name##3 -5, *+AR0(5), AR0 /* W,O,R */ &\
+ name##3 *+AR0(5), -5, AR0 /* O,W,R */ &\
+ name##3 *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
+ .endif
+
+
+/* T2: General 3-operand integer operation with 2 args
+ Syntax: <i> src2, src1
+ src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+ src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+ Instr: 1/0 - CMPI3
+ Alias: i, i3
+*/
+#define T2_CLASS(name) \
+name##_T2: &\
+ name AR2, AR1 /* E,G */ &\
+ name AR1, *+AR0(1) /* E,J */ &\
+ name *+AR0(1), AR1 /* I,G */ &\
+ name *+AR1(1), *+AR0(1) /* I,J */ &\
+ .ifdef TEST_C4X &\
+ name -5, AR1 /* W,G */ &\
+ name *+AR0(5), AR1 /* C,G */ &\
+ name -5, *+AR0(5) /* W,O */ &\
+ name *+AR0(5), *+AR1(5) /* C,O */ &\
+ .endif &\
+name##3_T2: &\
+ name##3 AR2, AR1 /* E,G */ &\
+ name##3 AR1, *+AR0(1) /* E,J */ &\
+ name##3 *+AR0(1), AR1 /* I,G */ &\
+ name##3 *+AR1(1), *+AR0(1) /* I,J */ &\
+ .ifdef TEST_C4X &\
+ name##3 -5, AR1 /* W,G */ &\
+ name##3 *+AR0(5), AR1 /* C,G */ &\
+ name##3 -5, *+AR0(5) /* W,O */ &\
+ name##3 *+AR0(5), *+AR1(5) /* C,O */ &\
+ .endif
+
+
+/* T2C: General commutative 3-operand integer operation with 2 args
+ Syntax: <i> src2, src1 - Manual
+ <i> src1, src2
+ src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+ src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0)
+ Instr: 1/0 - TSTB3
+ Alias: i, i3
+*/
+#define T2C_CLASS(name) \
+name##_T2C: &\
+ name AR2, AR1 /* E,G */ &\
+ name AR1, *+AR0(1) /* E,J */ &\
+ name *+AR0(1), AR1 /* I,G */ &\
+ name *+AR1(1), *+AR0(1) /* I,J */ &\
+ .ifdef TEST_C4X &\
+ name 5, AR1 /* W,G */ &\
+ name AR1, -5 /* G,W */ &\
+ name *+AR0(5), AR1 /* C,G */ &\
+ name AR1, *+AR0(5) /* G,C */ &\
+ name 5, *+AR0(5) /* W,O */ &\
+ name *+AR0(5), -5 /* O,W */ &\
+ name *+AR0(5), *+AR1(5) /* C,O */ &\
+ .endif &\
+name##3_T2C: &\
+ name##3 AR2, AR1 /* E,G */ &\
+ name##3 AR1, *+AR0(1) /* E,J */ &\
+ name##3 *+AR0(1), AR1 /* I,G */ &\
+ name##3 *+AR1(1), *+AR0(1) /* I,J */ &\
+ .ifdef TEST_C4X &\
+ name##3 -5, AR1 /* W,G */ &\
+ name##3 AR1, -5 /* G,W */ &\
+ name##3 *+AR0(5), AR1 /* C,G */ &\
+ name##3 AR1, *+AR0(5) /* G,C */ &\
+ name##3 -5, *+AR0(5) /* W,O */ &\
+ name##3 *+AR0(5), -5 /* O,W */ &\
+ name##3 *+AR0(5), *+AR1(5) /* C,O */ &\
+ .endif
--- /dev/null
+; File is autogenerated from allopcodes.S - do not edit
+; Please use ./rebuild.sh to rebuild this file
+
+;;;
+;;; Test all opcodes and argument permuation
+;;; To make our job a lot simpler, we define a couple of
+;;; insn classes, that we use to generate the proper
+;;; test output.
+;;;
+;;; To rebuild this file you must use
+;;; ./rebuild.sh
+;;;
+
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+ .text
+start: absf_B: & absf R1, R0 & absf R0 & absf @start, R0 & absf *+AR0(5), R0 & absf 3.5, R0
+ absf_stf_P: & absf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf *+AR0(1), R0
+ absi_A: & absi AR1, AR0 & absi AR0 & absi @start, AR0 & absi *+AR0(5), AR0 & absi -5, AR0
+ absi_sti_P: & absi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi *+AR0(1), R0
+ addc_A: & addc AR1, AR0 & addc AR0 & addc @start, AR0 & addc *+AR0(5), AR0 & addc -5, AR0
+ addc_TC: & addc AR2, AR1, AR0 & addc AR1, AR0 & addc AR1, *+AR0(1), AR0 & addc *+AR0(1), AR1, AR0 & addc *+AR0(1), AR0 & addc *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addc 5, AR1, AR0 & addc 5, AR0 & addc AR1, -5, AR0 & addc *+AR0(5), AR1, AR0 & addc *+AR0(5), AR0 & addc AR1, *+AR0(5), AR0 & addc 5, *+AR0(5), AR0 & addc *+AR0(5), -5, AR0 & addc *+AR0(5), *+AR1(5), AR0 & .endif & addc3_TC: & addc3 AR2, AR1, AR0 & addc3 AR1, AR0 & addc3 AR1, *+AR0(1), AR0 & addc3 *+AR0(1), AR1, AR0 & addc3 *+AR0(1), AR0 & addc3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addc3 -5, AR1, AR0 & addc3 -5, AR0 & addc3 AR1, -5, AR0 & addc3 *+AR0(5), AR1, AR0 & addc3 *+AR0(5), AR0 & addc3 AR1, *+AR0(5), AR0 & addc3 -5, *+AR0(5), AR0 & addc3 *+AR0(5), -5, AR0 & addc3 *+AR0(5), *+AR1(5), AR0 & .endif
+ addf_B: & addf R1, R0 & addf R0 & addf @start, R0 & addf *+AR0(5), R0 & addf 3.5, R0
+ addf_SC: & addf R2, R1, R0 & addf R1, R0 & addf R1, *+AR0(1), R0 & addf *+AR0(1), R1, R0 & addf *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & addf *+AR0(5), R1, R0 & addf *+AR0(5), R0 & addf R1, *+AR0(5), R0 & addf *+AR0(5), *+AR1(5), R0 & .endif & addf3_SC: & addf3 R2, R1, R0 & addf3 R1, R0 & addf3 R1, *+AR0(1), R0 & addf3 *+AR0(1), R1, R0 & addf3 *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & addf3 *+AR0(5), R1, R0 & addf3 *+AR0(5), R0 & addf3 R1, *+AR0(5), R0 & addf3 *+AR0(5), *+AR1(5), R0 & .endif
+ addf_stf_QC: & addf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf R0, *+AR0(1), R0 & addf3_stf_QC: & addf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf3 R0, *+AR0(1), R0
+ addi_A: & addi AR1, AR0 & addi AR0 & addi @start, AR0 & addi *+AR0(5), AR0 & addi -5, AR0
+ addi_TC: & addi AR2, AR1, AR0 & addi AR1, AR0 & addi AR1, *+AR0(1), AR0 & addi *+AR0(1), AR1, AR0 & addi *+AR0(1), AR0 & addi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addi 5, AR1, AR0 & addi 5, AR0 & addi AR1, -5, AR0 & addi *+AR0(5), AR1, AR0 & addi *+AR0(5), AR0 & addi AR1, *+AR0(5), AR0 & addi 5, *+AR0(5), AR0 & addi *+AR0(5), -5, AR0 & addi *+AR0(5), *+AR1(5), AR0 & .endif & addi3_TC: & addi3 AR2, AR1, AR0 & addi3 AR1, AR0 & addi3 AR1, *+AR0(1), AR0 & addi3 *+AR0(1), AR1, AR0 & addi3 *+AR0(1), AR0 & addi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addi3 -5, AR1, AR0 & addi3 -5, AR0 & addi3 AR1, -5, AR0 & addi3 *+AR0(5), AR1, AR0 & addi3 *+AR0(5), AR0 & addi3 AR1, *+AR0(5), AR0 & addi3 -5, *+AR0(5), AR0 & addi3 *+AR0(5), -5, AR0 & addi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ addi_sti_QC: & addi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi R0, *+AR0(1), R0 & addi3_sti_QC: & addi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi3 R0, *+AR0(1), R0
+ and_AU: & and AR1, AR0 & and AR0 & and @start, AR0 & and *+AR0(5), AR0 & and 5, AR0
+ and_TC: & and AR2, AR1, AR0 & and AR1, AR0 & and AR1, *+AR0(1), AR0 & and *+AR0(1), AR1, AR0 & and *+AR0(1), AR0 & and *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & and 5, AR1, AR0 & and 5, AR0 & and AR1, -5, AR0 & and *+AR0(5), AR1, AR0 & and *+AR0(5), AR0 & and AR1, *+AR0(5), AR0 & and 5, *+AR0(5), AR0 & and *+AR0(5), -5, AR0 & and *+AR0(5), *+AR1(5), AR0 & .endif & and3_TC: & and3 AR2, AR1, AR0 & and3 AR1, AR0 & and3 AR1, *+AR0(1), AR0 & and3 *+AR0(1), AR1, AR0 & and3 *+AR0(1), AR0 & and3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & and3 -5, AR1, AR0 & and3 -5, AR0 & and3 AR1, -5, AR0 & and3 *+AR0(5), AR1, AR0 & and3 *+AR0(5), AR0 & and3 AR1, *+AR0(5), AR0 & and3 -5, *+AR0(5), AR0 & and3 *+AR0(5), -5, AR0 & and3 *+AR0(5), *+AR1(5), AR0 & .endif
+ and_sti_QC: & and *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and *+AR0(1), R0 &|| sti R1, *+AR1(1) & and R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and *+AR0(1), R0 & sti R1, *+AR1(1) &|| and R0, *+AR0(1), R0 & and3_sti_QC: & and3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & and3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| and3 R0, *+AR0(1), R0
+ andn_AU: & andn AR1, AR0 & andn AR0 & andn @start, AR0 & andn *+AR0(5), AR0 & andn 5, AR0
+ andn_T: & andn AR2, AR1, AR0 & andn AR1, AR0 & andn AR1, *+AR0(1), AR0 & andn *+AR0(1), AR1, AR0 & andn *+AR0(1), AR0 & andn *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & andn 5, AR1, AR0 & andn 5, AR0 & andn *+AR0(5), AR1, AR0 & andn *+AR0(5), AR0 & andn 5, *+AR0(5), AR0 & andn *+AR0(5), *+AR1(5), AR0 & .endif & andn3_T: & andn3 AR2, AR1, AR0 & andn3 AR1, AR0 & andn3 AR1, *+AR0(1), AR0 & andn3 *+AR0(1), AR1, AR0 & andn3 *+AR0(1), AR0 & andn3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & andn3 -5, AR1, AR0 & andn3 -5, AR0 & andn3 *+AR0(5), AR1, AR0 & andn3 *+AR0(5), AR0 & andn3 -5, *+AR0(5), AR0 & andn3 *+AR0(5), *+AR1(5), AR0 & .endif
+ ash_A: & ash AR1, AR0 & ash AR0 & ash @start, AR0 & ash *+AR0(5), AR0 & ash -5, AR0
+ ash_T: & ash AR2, AR1, AR0 & ash AR1, AR0 & ash AR1, *+AR0(1), AR0 & ash *+AR0(1), AR1, AR0 & ash *+AR0(1), AR0 & ash *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & ash 5, AR1, AR0 & ash 5, AR0 & ash *+AR0(5), AR1, AR0 & ash *+AR0(5), AR0 & ash 5, *+AR0(5), AR0 & ash *+AR0(5), *+AR1(5), AR0 & .endif & ash3_T: & ash3 AR2, AR1, AR0 & ash3 AR1, AR0 & ash3 AR1, *+AR0(1), AR0 & ash3 *+AR0(1), AR1, AR0 & ash3 *+AR0(1), AR0 & ash3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & ash3 -5, AR1, AR0 & ash3 -5, AR0 & ash3 *+AR0(5), AR1, AR0 & ash3 *+AR0(5), AR0 & ash3 -5, *+AR0(5), AR0 & ash3 *+AR0(5), *+AR1(5), AR0 & .endif
+ ash_sti_Q: & ash R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, *+AR0(1), R0 & ash3_sti_Q: & ash3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash3 R0, *+AR0(1), R0
+ bC_J: & bC R0 & bC start & b_J: & b R0 & b start
+ bCd_J: & bCd R0 & bCd start & bd_J: & bd R0 & bd start
+br_I: br start
+brd_I: brd start
+call_I: call start
+call_JS: callc R0
+ callc start
+ cmpf_B: & cmpf R1, R0 & cmpf R0 & cmpf @start, R0 & cmpf *+AR0(5), R0 & cmpf 3.5, R0
+ cmpf_S2: & cmpf R2, R1 & cmpf R1, *+AR0(1) & cmpf *+AR0(1), R1 & cmpf *+AR0(1), *+AR1(1) & .ifdef TEST_C4X & cmpf *+AR0(5), R1 & cmpf *+AR0(5), *+AR1(5) & .endif & cmpf3_S2: & cmpf3 R2, R1 & cmpf3 R1, *+AR0(1) & cmpf3 *+AR0(1), R1 & cmpf3 *+AR0(1), *+AR1(1) & .ifdef TEST_C4X & cmpf3 *+AR0(5), R1 & cmpf3 *+AR0(5), *+AR1(5) & .endif
+ cmpi_A: & cmpi AR1, AR0 & cmpi AR0 & cmpi @start, AR0 & cmpi *+AR0(5), AR0 & cmpi -5, AR0
+ cmpi_T2: & cmpi AR2, AR1 & cmpi AR1, *+AR0(1) & cmpi *+AR0(1), AR1 & cmpi *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & cmpi -5, AR1 & cmpi *+AR0(5), AR1 & cmpi -5, *+AR0(5) & cmpi *+AR0(5), *+AR1(5) & .endif & cmpi3_T2: & cmpi3 AR2, AR1 & cmpi3 AR1, *+AR0(1) & cmpi3 *+AR0(1), AR1 & cmpi3 *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & cmpi3 -5, AR1 & cmpi3 *+AR0(5), AR1 & cmpi3 -5, *+AR0(5) & cmpi3 *+AR0(5), *+AR1(5) & .endif
+ dbC_D: & dbC AR0, R0 & dbC AR0, start & db_D: & db AR0, R0 & db AR0, start
+ dbCd_D: & dbCd AR0, R0 & dbCd AR0, start & dbd_D: & dbd AR0, R0 & dbd AR0, start
+ fix_AF: & fix R1, R0 & fix R0 & fix @start, AR0 & fix *+AR0(5), AR0 & fix 3.5, AR0
+ fix_sti_P: & fix *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| fix *+AR0(1), R0
+ float_BI: & float AR1, R0 & float R0 & float @start, R0 & float *+AR0(5), R0 & float -5, R0
+ float_stf_P: & float *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| float *+AR0(1), R0
+iack_Z: iack @start
+ iack *+AR0(1)
+idle_Z: idle
+ .ifdef TEST_IDLE2
+idle2_Z: idle2
+ .endif
+ lde_B: & lde R1, R0 & lde R0 & lde @start, R0 & lde *+AR0(5), R0 & lde 3.5, R0
+ ldf_B: & ldf R1, R0 & ldf R0 & ldf @start, R0 & ldf *+AR0(5), R0 & ldf 3.5, R0
+ ldf_LL: & ldf *+AR0(1), R0 &|| ldf *+AR1(1), R1 & ldf2 *+AR0(1), R0 &|| ldf1 *+AR1(1), R1 & ldf1 *+AR1(1), R1 &|| ldf2 *+AR0(1), R0
+ ldf_stf_P: & ldf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| ldf *+AR0(1), R0
+ ldfC_BB: & ldfC R1, R0 & ldfC R0 & ldfC @start, R0 & ldfC *+AR0(5), R0 & ldfC 3.5, R0
+ ldfi_B6: & ldfi @start, R0 & ldfi *+AR0(5), R0
+ ldi_A: & ldi AR1, AR0 & ldi AR0 & ldi @start, AR0 & ldi *+AR0(5), AR0 & ldi -5, AR0
+ ldi_LL: & ldi *+AR0(1), R0 &|| ldi *+AR1(1), R1 & ldi2 *+AR0(1), R0 &|| ldi1 *+AR1(1), R1 & ldi1 *+AR1(1), R1 &|| ldi2 *+AR0(1), R0
+ ldi_sti_P: & ldi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ldi *+AR0(1), R0
+ ldiC_AB: & ldiC AR1, AR0 & ldiC AR0 & ldiC @start, AR0 & ldiC *+AR0(5), AR0 & ldiC -5, AR0
+ ldii_A6: & ldii @start, AR0 & ldii *+AR0(5), AR0
+ldp_Z: ldp start
+ ldm_B: & ldm R1, R0 & ldm R0 & ldm @start, R0 & ldm *+AR0(5), R0 & ldm 3.5, R0
+ .ifdef TEST_LPWR
+lopower_Z: lopower
+ .endif
+ lsh_A: & lsh AR1, AR0 & lsh AR0 & lsh @start, AR0 & lsh *+AR0(5), AR0 & lsh -5, AR0
+ lsh_T: & lsh AR2, AR1, AR0 & lsh AR1, AR0 & lsh AR1, *+AR0(1), AR0 & lsh *+AR0(1), AR1, AR0 & lsh *+AR0(1), AR0 & lsh *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & lsh 5, AR1, AR0 & lsh 5, AR0 & lsh *+AR0(5), AR1, AR0 & lsh *+AR0(5), AR0 & lsh 5, *+AR0(5), AR0 & lsh *+AR0(5), *+AR1(5), AR0 & .endif & lsh3_T: & lsh3 AR2, AR1, AR0 & lsh3 AR1, AR0 & lsh3 AR1, *+AR0(1), AR0 & lsh3 *+AR0(1), AR1, AR0 & lsh3 *+AR0(1), AR0 & lsh3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & lsh3 -5, AR1, AR0 & lsh3 -5, AR0 & lsh3 *+AR0(5), AR1, AR0 & lsh3 *+AR0(5), AR0 & lsh3 -5, *+AR0(5), AR0 & lsh3 *+AR0(5), *+AR1(5), AR0 & .endif
+ lsh_sti_Q: & lsh R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh R0, *+AR0(1), R0 & lsh3_sti_Q: & lsh3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh3 R0, *+AR0(1), R0
+ .ifdef TEST_LPWR
+maxspeed_Z: maxspeed
+ .endif
+ mpyf_B: & mpyf R1, R0 & mpyf R0 & mpyf @start, R0 & mpyf *+AR0(5), R0 & mpyf 3.5, R0
+ mpyf_SC: & mpyf R2, R1, R0 & mpyf R1, R0 & mpyf R1, *+AR0(1), R0 & mpyf *+AR0(1), R1, R0 & mpyf *+AR0(1), R0 & mpyf *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & mpyf *+AR0(5), R1, R0 & mpyf *+AR0(5), R0 & mpyf R1, *+AR0(5), R0 & mpyf *+AR0(5), *+AR1(5), R0 & .endif & mpyf3_SC: & mpyf3 R2, R1, R0 & mpyf3 R1, R0 & mpyf3 R1, *+AR0(1), R0 & mpyf3 *+AR0(1), R1, R0 & mpyf3 *+AR0(1), R0 & mpyf3 *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & mpyf3 *+AR0(5), R1, R0 & mpyf3 *+AR0(5), R0 & mpyf3 R1, *+AR0(5), R0 & mpyf3 *+AR0(5), *+AR1(5), R0 & .endif
+ mpyf_addf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf3_addf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf_addf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf3_addf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & addf_mpyf_M: & addf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf3_mpyf3_M: & addf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf_mpyf3_M: & addf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3_mpyf_M: & addf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 &
+ mpyf_stf_QC: & mpyf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf R0, *+AR0(1), R0 & mpyf3_stf_QC: & mpyf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf3 R0, *+AR0(1), R0
+ mpyf_subf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf3_subf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf_subf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf3_subf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & subf_mpyf_M: & subf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf3_mpyf3_M: & subf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf_mpyf3_M: & subf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3_mpyf_M: & subf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 &
+ mpyi_A: & mpyi AR1, AR0 & mpyi AR0 & mpyi @start, AR0 & mpyi *+AR0(5), AR0 & mpyi -5, AR0
+ mpyi_TC: & mpyi AR2, AR1, AR0 & mpyi AR1, AR0 & mpyi AR1, *+AR0(1), AR0 & mpyi *+AR0(1), AR1, AR0 & mpyi *+AR0(1), AR0 & mpyi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyi 5, AR1, AR0 & mpyi 5, AR0 & mpyi AR1, -5, AR0 & mpyi *+AR0(5), AR1, AR0 & mpyi *+AR0(5), AR0 & mpyi AR1, *+AR0(5), AR0 & mpyi 5, *+AR0(5), AR0 & mpyi *+AR0(5), -5, AR0 & mpyi *+AR0(5), *+AR1(5), AR0 & .endif & mpyi3_TC: & mpyi3 AR2, AR1, AR0 & mpyi3 AR1, AR0 & mpyi3 AR1, *+AR0(1), AR0 & mpyi3 *+AR0(1), AR1, AR0 & mpyi3 *+AR0(1), AR0 & mpyi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyi3 -5, AR1, AR0 & mpyi3 -5, AR0 & mpyi3 AR1, -5, AR0 & mpyi3 *+AR0(5), AR1, AR0 & mpyi3 *+AR0(5), AR0 & mpyi3 AR1, *+AR0(5), AR0 & mpyi3 -5, *+AR0(5), AR0 & mpyi3 *+AR0(5), -5, AR0 & mpyi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ mpyi_addi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi3_addi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi_addi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi3_addi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & addi_mpyi_M: & addi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi3_mpyi3_M: & addi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi_mpyi3_M: & addi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3_mpyi_M: & addi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 &
+ mpyi_sti_QC: & mpyi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi R0, *+AR0(1), R0 & mpyi3_sti_QC: & mpyi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi3 R0, *+AR0(1), R0
+ mpyi_subi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi3_subi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi_subi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi3_subi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & subi_mpyi_M: & subi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi3_mpyi3_M: & subi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi_mpyi3_M: & subi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3_mpyi_M: & subi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 &
+ negb_A: & negb AR1, AR0 & negb AR0 & negb @start, AR0 & negb *+AR0(5), AR0 & negb -5, AR0
+ negf_B: & negf R1, R0 & negf R0 & negf @start, R0 & negf *+AR0(5), R0 & negf 3.5, R0
+ negf_stf_P: & negf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| negf *+AR0(1), R0
+ negi_A: & negi AR1, AR0 & negi AR0 & negi @start, AR0 & negi *+AR0(5), AR0 & negi -5, AR0
+ negi_sti_P: & negi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| negi *+AR0(1), R0
+ nop_A2: & nop AR0 & nop *+AR0(5) & nop
+ norm_B: & norm R1, R0 & norm R0 & norm @start, R0 & norm *+AR0(5), R0 & norm 3.5, R0
+ not_AU: & not AR1, AR0 & not AR0 & not @start, AR0 & not *+AR0(5), AR0 & not 5, AR0
+ not_sti_P: & not *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| not *+AR0(1), R0
+ or_AU: & or AR1, AR0 & or AR0 & or @start, AR0 & or *+AR0(5), AR0 & or 5, AR0
+ or_TC: & or AR2, AR1, AR0 & or AR1, AR0 & or AR1, *+AR0(1), AR0 & or *+AR0(1), AR1, AR0 & or *+AR0(1), AR0 & or *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & or 5, AR1, AR0 & or 5, AR0 & or AR1, -5, AR0 & or *+AR0(5), AR1, AR0 & or *+AR0(5), AR0 & or AR1, *+AR0(5), AR0 & or 5, *+AR0(5), AR0 & or *+AR0(5), -5, AR0 & or *+AR0(5), *+AR1(5), AR0 & .endif & or3_TC: & or3 AR2, AR1, AR0 & or3 AR1, AR0 & or3 AR1, *+AR0(1), AR0 & or3 *+AR0(1), AR1, AR0 & or3 *+AR0(1), AR0 & or3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & or3 -5, AR1, AR0 & or3 -5, AR0 & or3 AR1, -5, AR0 & or3 *+AR0(5), AR1, AR0 & or3 *+AR0(5), AR0 & or3 AR1, *+AR0(5), AR0 & or3 -5, *+AR0(5), AR0 & or3 *+AR0(5), -5, AR0 & or3 *+AR0(5), *+AR1(5), AR0 & .endif
+ or_sti_QC: & or *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or *+AR0(1), R0 &|| sti R1, *+AR1(1) & or R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or *+AR0(1), R0 & sti R1, *+AR1(1) &|| or R0, *+AR0(1), R0 & or3_sti_QC: & or3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & or3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| or3 R0, *+AR0(1), R0
+ pop_R: & pop AR0
+ popf_RF: & popf F0
+ push_R: & push AR0
+ pushf_RF: & pushf F0
+reti_Z: retiC
+ reti
+rets_Z: retsC
+ rets
+ rnd_B: & rnd R1, R0 & rnd R0 & rnd @start, R0 & rnd *+AR0(5), R0 & rnd 3.5, R0
+ rol_R: & rol AR0
+ rolc_R: & rolc AR0
+ ror_R: & ror AR0
+ rorc_R: & rorc AR0
+rptb_I2: rptb start
+ rpts_A3: & rpts AR1 & rpts @start & rpts *+AR0(5) & rpts 5
+sigi_Z: sigi
+ stf_B7: & stf R0, @start & stf R0, *+AR0(5)
+ stf_LS: & stf R0, *+AR0(1) &|| stf R1, *+AR1(1) & stf2 R0, *+AR0(1) &|| stf1 R1, *+AR1(1) & stf1 R1, *+AR1(1) &|| stf2 R0, *+AR0(1)
+ stfi_B7: & stfi R0, @start & stfi R0, *+AR0(5)
+ sti_A7: & sti AR0, @start & sti AR0, *+AR0(5)
+ sti_LS: & sti R0, *+AR0(1) &|| sti R1, *+AR1(1) & sti2 R0, *+AR0(1) &|| sti1 R1, *+AR1(1) & sti1 R1, *+AR1(1) &|| sti2 R0, *+AR0(1)
+ stii_A7: & stii AR0, @start & stii AR0, *+AR0(5)
+ subb_A: & subb AR1, AR0 & subb AR0 & subb @start, AR0 & subb *+AR0(5), AR0 & subb -5, AR0
+ subb_T: & subb AR2, AR1, AR0 & subb AR1, AR0 & subb AR1, *+AR0(1), AR0 & subb *+AR0(1), AR1, AR0 & subb *+AR0(1), AR0 & subb *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subb 5, AR1, AR0 & subb 5, AR0 & subb *+AR0(5), AR1, AR0 & subb *+AR0(5), AR0 & subb 5, *+AR0(5), AR0 & subb *+AR0(5), *+AR1(5), AR0 & .endif & subb3_T: & subb3 AR2, AR1, AR0 & subb3 AR1, AR0 & subb3 AR1, *+AR0(1), AR0 & subb3 *+AR0(1), AR1, AR0 & subb3 *+AR0(1), AR0 & subb3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subb3 -5, AR1, AR0 & subb3 -5, AR0 & subb3 *+AR0(5), AR1, AR0 & subb3 *+AR0(5), AR0 & subb3 -5, *+AR0(5), AR0 & subb3 *+AR0(5), *+AR1(5), AR0 & .endif
+ subc_A: & subc AR1, AR0 & subc AR0 & subc @start, AR0 & subc *+AR0(5), AR0 & subc -5, AR0
+ subf_B: & subf R1, R0 & subf R0 & subf @start, R0 & subf *+AR0(5), R0 & subf 3.5, R0
+ subf_S: & subf R2, R1, R0 & subf R1, R0 & subf R1, *+AR0(1), R0 & subf *+AR0(1), R1, R0 & subf *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & subf *+AR0(5), R1, R0 & subf *+AR0(5), R0 & subf *+AR0(5), *+AR1(5), R0 & .endif & subf3_S: & subf3 R2, R1, R0 & subf3 R1, R0 & subf3 R1, *+AR0(1), R0 & subf3 *+AR0(1), R1, R0 & subf3 *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & subf3 *+AR0(5), R1, R0 & subf3 *+AR0(5), R0 & subf3 *+AR0(5), *+AR1(5), R0 & .endif
+ subf_stf_Q: & subf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf R0, *+AR0(1), R0 & subf3_stf_Q: & subf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf3 R0, *+AR0(1), R0
+ subi_A: & subi AR1, AR0 & subi AR0 & subi @start, AR0 & subi *+AR0(5), AR0 & subi -5, AR0
+ subi_T: & subi AR2, AR1, AR0 & subi AR1, AR0 & subi AR1, *+AR0(1), AR0 & subi *+AR0(1), AR1, AR0 & subi *+AR0(1), AR0 & subi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subi 5, AR1, AR0 & subi 5, AR0 & subi *+AR0(5), AR1, AR0 & subi *+AR0(5), AR0 & subi 5, *+AR0(5), AR0 & subi *+AR0(5), *+AR1(5), AR0 & .endif & subi3_T: & subi3 AR2, AR1, AR0 & subi3 AR1, AR0 & subi3 AR1, *+AR0(1), AR0 & subi3 *+AR0(1), AR1, AR0 & subi3 *+AR0(1), AR0 & subi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subi3 -5, AR1, AR0 & subi3 -5, AR0 & subi3 *+AR0(5), AR1, AR0 & subi3 *+AR0(5), AR0 & subi3 -5, *+AR0(5), AR0 & subi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ subi_sti_Q: & subi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi R0, *+AR0(1), R0 & subi3_sti_Q: & subi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi3 R0, *+AR0(1), R0
+ subrb_A: & subrb AR1, AR0 & subrb AR0 & subrb @start, AR0 & subrb *+AR0(5), AR0 & subrb -5, AR0
+ subrf_B: & subrf R1, R0 & subrf R0 & subrf @start, R0 & subrf *+AR0(5), R0 & subrf 3.5, R0
+ subri_A: & subri AR1, AR0 & subri AR0 & subri @start, AR0 & subri *+AR0(5), AR0 & subri -5, AR0
+swi_Z: swi
+trap_Z: trapC 10
+ trap 10
+ tstb_AU: & tstb AR1, AR0 & tstb AR0 & tstb @start, AR0 & tstb *+AR0(5), AR0 & tstb 5, AR0
+ tstb_T2C: & tstb AR2, AR1 & tstb AR1, *+AR0(1) & tstb *+AR0(1), AR1 & tstb *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & tstb 5, AR1 & tstb AR1, -5 & tstb *+AR0(5), AR1 & tstb AR1, *+AR0(5) & tstb 5, *+AR0(5) & tstb *+AR0(5), -5 & tstb *+AR0(5), *+AR1(5) & .endif & tstb3_T2C: & tstb3 AR2, AR1 & tstb3 AR1, *+AR0(1) & tstb3 *+AR0(1), AR1 & tstb3 *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & tstb3 -5, AR1 & tstb3 AR1, -5 & tstb3 *+AR0(5), AR1 & tstb3 AR1, *+AR0(5) & tstb3 -5, *+AR0(5) & tstb3 *+AR0(5), -5 & tstb3 *+AR0(5), *+AR1(5) & .endif
+ xor_AU: & xor AR1, AR0 & xor AR0 & xor @start, AR0 & xor *+AR0(5), AR0 & xor 5, AR0
+ xor_TC: & xor AR2, AR1, AR0 & xor AR1, AR0 & xor AR1, *+AR0(1), AR0 & xor *+AR0(1), AR1, AR0 & xor *+AR0(1), AR0 & xor *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & xor 5, AR1, AR0 & xor 5, AR0 & xor AR1, -5, AR0 & xor *+AR0(5), AR1, AR0 & xor *+AR0(5), AR0 & xor AR1, *+AR0(5), AR0 & xor 5, *+AR0(5), AR0 & xor *+AR0(5), -5, AR0 & xor *+AR0(5), *+AR1(5), AR0 & .endif & xor3_TC: & xor3 AR2, AR1, AR0 & xor3 AR1, AR0 & xor3 AR1, *+AR0(1), AR0 & xor3 *+AR0(1), AR1, AR0 & xor3 *+AR0(1), AR0 & xor3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & xor3 -5, AR1, AR0 & xor3 -5, AR0 & xor3 AR1, -5, AR0 & xor3 *+AR0(5), AR1, AR0 & xor3 *+AR0(5), AR0 & xor3 AR1, *+AR0(5), AR0 & xor3 -5, *+AR0(5), AR0 & xor3 *+AR0(5), -5, AR0 & xor3 *+AR0(5), *+AR1(5), AR0 & .endif
+ xor_sti_QC: & xor *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor R0, *+AR0(1), R0 & xor3_sti_QC: & xor3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor3 R0, *+AR0(1), R0
+
+ .ifdef TEST_C4X
+ bCaf_J: & bCaf R0 & bCaf start & baf_J: & baf R0 & baf start
+ bCat_J: & bCat R0 & bCat start & bat_J: & bat R0 & bat start
+ frieee_B6: & frieee @start, R0 & frieee *+AR0(5), R0
+ frieee_stf_P: & frieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| frieee *+AR0(1), R0
+laj_I: laj start
+laj_JS: lajc R0
+ lajc start
+lat_Z: latC 10
+ lb0_A: & lb0 AR1, AR0 & lb0 AR0 & lb0 @start, AR0 & lb0 *+AR0(5), AR0 & lb0 -5, AR0
+ lb1_A: & lb1 AR1, AR0 & lb1 AR0 & lb1 @start, AR0 & lb1 *+AR0(5), AR0 & lb1 -5, AR0
+ lb2_A: & lb2 AR1, AR0 & lb2 AR0 & lb2 @start, AR0 & lb2 *+AR0(5), AR0 & lb2 -5, AR0
+ lb3_A: & lb3 AR1, AR0 & lb3 AR0 & lb3 @start, AR0 & lb3 *+AR0(5), AR0 & lb3 -5, AR0
+ lbu0_AU: & lbu0 AR1, AR0 & lbu0 AR0 & lbu0 @start, AR0 & lbu0 *+AR0(5), AR0 & lbu0 5, AR0
+ lbu1_AU: & lbu1 AR1, AR0 & lbu1 AR0 & lbu1 @start, AR0 & lbu1 *+AR0(5), AR0 & lbu1 5, AR0
+ lbu2_AU: & lbu2 AR1, AR0 & lbu2 AR0 & lbu2 @start, AR0 & lbu2 *+AR0(5), AR0 & lbu2 5, AR0
+ lbu3_AU: & lbu3 AR1, AR0 & lbu3 AR0 & lbu3 @start, AR0 & lbu3 *+AR0(5), AR0 & lbu3 5, AR0
+ lda_AY: & lda AR1, AR0 & lda @start, AR0 & lda *+AR0(5), AR0 & lda -5, AR0
+ldep_Z: ldep IVTP, AR0
+ldhi_Z: ldhi 35, R0
+ ldhi start, R0
+ldpe_Z: ldpe AR0, IVTP
+ldpk_Z: ldpk start
+ lh0_A: & lh0 AR1, AR0 & lh0 AR0 & lh0 @start, AR0 & lh0 *+AR0(5), AR0 & lh0 -5, AR0
+ lh1_A: & lh1 AR1, AR0 & lh1 AR0 & lh1 @start, AR0 & lh1 *+AR0(5), AR0 & lh1 -5, AR0
+ lhu0_AU: & lhu0 AR1, AR0 & lhu0 AR0 & lhu0 @start, AR0 & lhu0 *+AR0(5), AR0 & lhu0 5, AR0
+ lhu1_AU: & lhu1 AR1, AR0 & lhu1 AR0 & lhu1 @start, AR0 & lhu1 *+AR0(5), AR0 & lhu1 5, AR0
+ lwl0_A: & lwl0 AR1, AR0 & lwl0 AR0 & lwl0 @start, AR0 & lwl0 *+AR0(5), AR0 & lwl0 -5, AR0
+ lwl1_A: & lwl1 AR1, AR0 & lwl1 AR0 & lwl1 @start, AR0 & lwl1 *+AR0(5), AR0 & lwl1 -5, AR0
+ lwl2_A: & lwl2 AR1, AR0 & lwl2 AR0 & lwl2 @start, AR0 & lwl2 *+AR0(5), AR0 & lwl2 -5, AR0
+ lwl3_A: & lwl3 AR1, AR0 & lwl3 AR0 & lwl3 @start, AR0 & lwl3 *+AR0(5), AR0 & lwl3 -5, AR0
+ lwr0_A: & lwr0 AR1, AR0 & lwr0 AR0 & lwr0 @start, AR0 & lwr0 *+AR0(5), AR0 & lwr0 -5, AR0
+ lwr1_A: & lwr1 AR1, AR0 & lwr1 AR0 & lwr1 @start, AR0 & lwr1 *+AR0(5), AR0 & lwr1 -5, AR0
+ lwr2_A: & lwr2 AR1, AR0 & lwr2 AR0 & lwr2 @start, AR0 & lwr2 *+AR0(5), AR0 & lwr2 -5, AR0
+ lwr3_A: & lwr3 AR1, AR0 & lwr3 AR0 & lwr3 @start, AR0 & lwr3 *+AR0(5), AR0 & lwr3 -5, AR0
+ mb0_A: & mb0 AR1, AR0 & mb0 AR0 & mb0 @start, AR0 & mb0 *+AR0(5), AR0 & mb0 -5, AR0
+ mb1_A: & mb1 AR1, AR0 & mb1 AR0 & mb1 @start, AR0 & mb1 *+AR0(5), AR0 & mb1 -5, AR0
+ mb2_A: & mb2 AR1, AR0 & mb2 AR0 & mb2 @start, AR0 & mb2 *+AR0(5), AR0 & mb2 -5, AR0
+ mb3_A: & mb3 AR1, AR0 & mb3 AR0 & mb3 @start, AR0 & mb3 *+AR0(5), AR0 & mb3 -5, AR0
+ mh0_A: & mh0 AR1, AR0 & mh0 AR0 & mh0 @start, AR0 & mh0 *+AR0(5), AR0 & mh0 -5, AR0
+ mh1_A: & mh1 AR1, AR0 & mh1 AR0 & mh1 @start, AR0 & mh1 *+AR0(5), AR0 & mh1 -5, AR0
+ mh2_A: & mh2 AR1, AR0 & mh2 AR0 & mh2 @start, AR0 & mh2 *+AR0(5), AR0 & mh2 -5, AR0
+ mh3_A: & mh3 AR1, AR0 & mh3 AR0 & mh3 @start, AR0 & mh3 *+AR0(5), AR0 & mh3 -5, AR0
+ mpyshi_A: & mpyshi AR1, AR0 & mpyshi AR0 & mpyshi @start, AR0 & mpyshi *+AR0(5), AR0 & mpyshi -5, AR0
+ mpyshi_TC: & mpyshi AR2, AR1, AR0 & mpyshi AR1, AR0 & mpyshi AR1, *+AR0(1), AR0 & mpyshi *+AR0(1), AR1, AR0 & mpyshi *+AR0(1), AR0 & mpyshi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyshi 5, AR1, AR0 & mpyshi 5, AR0 & mpyshi AR1, -5, AR0 & mpyshi *+AR0(5), AR1, AR0 & mpyshi *+AR0(5), AR0 & mpyshi AR1, *+AR0(5), AR0 & mpyshi 5, *+AR0(5), AR0 & mpyshi *+AR0(5), -5, AR0 & mpyshi *+AR0(5), *+AR1(5), AR0 & .endif & mpyshi3_TC: & mpyshi3 AR2, AR1, AR0 & mpyshi3 AR1, AR0 & mpyshi3 AR1, *+AR0(1), AR0 & mpyshi3 *+AR0(1), AR1, AR0 & mpyshi3 *+AR0(1), AR0 & mpyshi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyshi3 -5, AR1, AR0 & mpyshi3 -5, AR0 & mpyshi3 AR1, -5, AR0 & mpyshi3 *+AR0(5), AR1, AR0 & mpyshi3 *+AR0(5), AR0 & mpyshi3 AR1, *+AR0(5), AR0 & mpyshi3 -5, *+AR0(5), AR0 & mpyshi3 *+AR0(5), -5, AR0 & mpyshi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ mpyuhi_A: & mpyuhi AR1, AR0 & mpyuhi AR0 & mpyuhi @start, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi -5, AR0
+ mpyuhi_TC: & mpyuhi AR2, AR1, AR0 & mpyuhi AR1, AR0 & mpyuhi AR1, *+AR0(1), AR0 & mpyuhi *+AR0(1), AR1, AR0 & mpyuhi *+AR0(1), AR0 & mpyuhi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyuhi 5, AR1, AR0 & mpyuhi 5, AR0 & mpyuhi AR1, -5, AR0 & mpyuhi *+AR0(5), AR1, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi AR1, *+AR0(5), AR0 & mpyuhi 5, *+AR0(5), AR0 & mpyuhi *+AR0(5), -5, AR0 & mpyuhi *+AR0(5), *+AR1(5), AR0 & .endif & mpyuhi3_TC: & mpyuhi3 AR2, AR1, AR0 & mpyuhi3 AR1, AR0 & mpyuhi3 AR1, *+AR0(1), AR0 & mpyuhi3 *+AR0(1), AR1, AR0 & mpyuhi3 *+AR0(1), AR0 & mpyuhi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyuhi3 -5, AR1, AR0 & mpyuhi3 -5, AR0 & mpyuhi3 AR1, -5, AR0 & mpyuhi3 *+AR0(5), AR1, AR0 & mpyuhi3 *+AR0(5), AR0 & mpyuhi3 AR1, *+AR0(5), AR0 & mpyuhi3 -5, *+AR0(5), AR0 & mpyuhi3 *+AR0(5), -5, AR0 & mpyuhi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ rcpf_BA: & rcpf AR1, R0 & rcpf R0 & rcpf @start, R0 & rcpf *+AR0(5), R0 & rcpf 3.5, R0
+retid_Z: retiCd
+ retid
+rptb2_I2: rptb AR0
+rptbd_I2: rptbd start
+ rptbd AR0
+ rsqrf_B: & rsqrf R1, R0 & rsqrf R0 & rsqrf @start, R0 & rsqrf *+AR0(5), R0 & rsqrf 3.5, R0
+ sigi_A6: & sigi @start, AR0 & sigi *+AR0(5), AR0
+sti2_A7: sti -5, @start
+ sti -5, *+AR0(5)
+stik_Z: stik -5, @start
+ stik -5, *+AR0(5)
+ toieee_B: & toieee R1, R0 & toieee R0 & toieee @start, R0 & toieee *+AR0(5), R0 & toieee 3.5, R0
+ toieee_stf_P: & toieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| toieee *+AR0(1), R0
+ .endif
+ .end
+
--- /dev/null
+#as: -m30 --defsym TEST_C3X=1
+#objdump: -d -z
+#name: c3x opcodes
+#source: opcodes.s
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <absf_B>:
+ 0: 00000001.*
+ 1: 00000000.*
+ 2: 00200000.*
+ 3: 00400005.*
+ 4: 00601600.*
+
+00000005 <absf_stf_P>:
+ 5: c8010100.*
+ 6: c8010100.*
+
+00000007 <absi_A>:
+ 7: 00880009.*
+ 8: 00880008.*
+ 9: 00a80000.*
+ a: 00c80005.*
+ b: 00e8fffb.*
+
+0000000c <absi_sti_P>:
+ c: ca010100.*
+ d: ca010100.*
+
+0000000e <addc_A>:
+ e: 01080009.*
+ f: 01080008.*
+ 10: 01280000.*
+ 11: 01480005.*
+ 12: 0168fffb.*
+
+00000013 <addc_TC>:
+ 13: 2008090a.*
+ 14: 01080009.*
+ 15: 20280009.*
+ 16: 20480900.*
+ 17: 01480001.*
+ 18: 20680001.*
+
+00000019 <addc3_TC>:
+ 19: 2008090a.*
+ 1a: 20080809.*
+ 1b: 20280009.*
+ 1c: 20480900.*
+ 1d: 20480800.*
+ 1e: 20680001.*
+
+0000001f <addf_B>:
+ 1f: 01800001.*
+ 20: 01800000.*
+ 21: 01a00000.*
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+ 2b0: 8e020100.*
+ 2b1: 8f0b0001.*
+ 2b2: 8f030001.*
+ 2b3: 8f0a0001.*
+ 2b4: 8f020001.*
+ 2b5: 8f000001.*
+ 2b6: 8f020001.*
+
+000002b7 <mpyi3_subi3_M>:
+ 2b7: 8c080100.*
+ 2b8: 8c100100.*
+ 2b9: 8d000001.*
+ 2ba: 8d000001.*
+ 2bb: 8d000001.*
+ 2bc: 8e0a0100.*
+ 2bd: 8e020100.*
+ 2be: 8f0b0001.*
+ 2bf: 8f030001.*
+ 2c0: 8f0a0001.*
+ 2c1: 8f020001.*
+ 2c2: 8f000001.*
+ 2c3: 8f020001.*
+
+000002c4 <subi_mpyi_M>:
+ 2c4: 8c080100.*
+ 2c5: 8c100100.*
+ 2c6: 8d000001.*
+ 2c7: 8d000001.*
+ 2c8: 8d000001.*
+ 2c9: 8e0a0100.*
+ 2ca: 8e020100.*
+ 2cb: 8f0b0001.*
+ 2cc: 8f030001.*
+ 2cd: 8f0a0001.*
+ 2ce: 8f020001.*
+ 2cf: 8f000001.*
+ 2d0: 8f020001.*
+
+000002d1 <subi3_mpyi3_M>:
+ 2d1: 8c080100.*
+ 2d2: 8c100100.*
+ 2d3: 8d000001.*
+ 2d4: 8d000001.*
+ 2d5: 8d000001.*
+ 2d6: 8e0a0100.*
+ 2d7: 8e020100.*
+ 2d8: 8f0b0001.*
+ 2d9: 8f030001.*
+ 2da: 8f0a0001.*
+ 2db: 8f020001.*
+ 2dc: 8f000001.*
+ 2dd: 8f020001.*
+
+000002de <subi_mpyi3_M>:
+ 2de: 8c080100.*
+ 2df: 8c100100.*
+ 2e0: 8d000001.*
+ 2e1: 8d000001.*
+ 2e2: 8d000001.*
+ 2e3: 8e0a0100.*
+ 2e4: 8e020100.*
+ 2e5: 8f0b0001.*
+ 2e6: 8f030001.*
+ 2e7: 8f0a0001.*
+ 2e8: 8f020001.*
+ 2e9: 8f000001.*
+ 2ea: 8f020001.*
+
+000002eb <subi3_mpyi_M>:
+ 2eb: 8c080100.*
+ 2ec: 8c100100.*
+ 2ed: 8d000001.*
+ 2ee: 8d000001.*
+ 2ef: 8d000001.*
+ 2f0: 8e0a0100.*
+ 2f1: 8e020100.*
+ 2f2: 8f0b0001.*
+ 2f3: 8f030001.*
+ 2f4: 8f0a0001.*
+ 2f5: 8f020001.*
+ 2f6: 8f000001.*
+ 2f7: 8f020001.*
+
+000002f8 <negb_A>:
+ 2f8: 0b080009.*
+ 2f9: 0b080008.*
+ 2fa: 0b280000.*
+ 2fb: 0b480005.*
+ 2fc: 0b68fffb.*
+
+000002fd <negf_B>:
+ 2fd: 0b800001.*
+ 2fe: 0b800000.*
+ 2ff: 0ba00000.*
+ 300: 0bc00005.*
+ 301: 0be01600.*
+
+00000302 <negf_stf_P>:
+ 302: e2010100.*
+ 303: e2010100.*
+
+00000304 <negi_A>:
+ 304: 0c080009.*
+ 305: 0c080008.*
+ 306: 0c280000.*
+ 307: 0c480005.*
+ 308: 0c68fffb.*
+
+00000309 <negi_sti_P>:
+ 309: e4010100.*
+ 30a: e4010100.*
+
+0000030b <nop_A2>:
+ 30b: 0c800008.*
+ 30c: 0cc00005.*
+ 30d: 0c800000.*
+
+0000030e <norm_B>:
+ 30e: 0d000001.*
+ 30f: 0d000000.*
+ 310: 0d200000.*
+ 311: 0d400005.*
+ 312: 0d601600.*
+
+00000313 <not_AU>:
+ 313: 0d880009.*
+ 314: 0d880008.*
+ 315: 0da80000.*
+ 316: 0dc80005.*
+ 317: 0de80005.*
+
+00000318 <not_sti_P>:
+ 318: e6010100.*
+ 319: e6010100.*
+
+0000031a <or_AU>:
+ 31a: 10080009.*
+ 31b: 10080008.*
+ 31c: 10280000.*
+ 31d: 10480005.*
+ 31e: 10680005.*
+
+0000031f <or_TC>:
+ 31f: 2588090a.*
+ 320: 10080009.*
+ 321: 25a80009.*
+ 322: 25c80900.*
+ 323: 10480001.*
+ 324: 25e80001.*
+
+00000325 <or3_TC>:
+ 325: 2588090a.*
+ 326: 25880809.*
+ 327: 25a80009.*
+ 328: 25c80900.*
+ 329: 25c80800.*
+ 32a: 25e80001.*
+
+0000032b <or_sti_QC>:
+ 32b: e8090100.*
+ 32c: e8010100.*
+ 32d: e8010100.*
+ 32e: e8090100.*
+ 32f: e8010100.*
+ 330: e8010100.*
+
+00000331 <or3_sti_QC>:
+ 331: e8090100.*
+ 332: e8010100.*
+ 333: e8010100.*
+ 334: e8090100.*
+ 335: e8010100.*
+ 336: e8010100.*
+
+00000337 <pop_R>:
+ 337: 0e280000.*
+
+00000338 <popf_RF>:
+ 338: 0ea00000.*
+
+00000339 <push_R>:
+ 339: 0f280000.*
+
+0000033a <pushf_RF>:
+ 33a: 0fa00000.*
+
+0000033b <reti_Z>:
+ 33b: 78010000.*
+ 33c: 78000000.*
+
+0000033d <rets_Z>:
+ 33d: 78810000.*
+ 33e: 78800000.*
+
+0000033f <rnd_B>:
+ 33f: 11000001.*
+ 340: 11000000.*
+ 341: 11200000.*
+ 342: 11400005.*
+ 343: 11601600.*
+
+00000344 <rol_R>:
+ 344: 11e80001.*
+
+00000345 <rolc_R>:
+ 345: 12680001.*
+
+00000346 <ror_R>:
+ 346: 12e8ffff.*
+
+00000347 <rorc_R>:
+ 347: 1368ffff.*
+
+00000348 <rptb_I2>:
+ 348: 64000000.*
+
+00000349 <rpts_A3>:
+ 349: 139b0009.*
+ 34a: 13bb0000.*
+ 34b: 13db0005.*
+ 34c: 13fb0005.*
+
+0000034d <sigi_Z>:
+ 34d: 16000000.*
+
+0000034e <stf_B7>:
+ 34e: 14200000.*
+ 34f: 14400005.*
+
+00000350 <stf_LS>:
+ 350: c0010100.*
+ 351: c0010100.*
+ 352: c0010100.*
+
+00000353 <stfi_B7>:
+ 353: 14a00000.*
+ 354: 14c00005.*
+
+00000355 <sti_A7>:
+ 355: 15280000.*
+ 356: 15480005.*
+
+00000357 <sti_LS>:
+ 357: c2010100.*
+ 358: c2010100.*
+ 359: c2010100.*
+
+0000035a <stii_A7>:
+ 35a: 15a80000.*
+ 35b: 15c80005.*
+
+0000035c <subb_A>:
+ 35c: 16880009.*
+ 35d: 16880008.*
+ 35e: 16a80000.*
+ 35f: 16c80005.*
+ 360: 16e8fffb.*
+
+00000361 <subb_T>:
+ 361: 2608090a.*
+ 362: 16880009.*
+ 363: 26280009.*
+ 364: 26480900.*
+ 365: 16c80001.*
+ 366: 26680001.*
+
+00000367 <subb3_T>:
+ 367: 2608090a.*
+ 368: 26080809.*
+ 369: 26280009.*
+ 36a: 26480900.*
+ 36b: 26480800.*
+ 36c: 26680001.*
+
+0000036d <subc_A>:
+ 36d: 17080009.*
+ 36e: 17080008.*
+ 36f: 17280000.*
+ 370: 17480005.*
+ 371: 1768fffb.*
+
+00000372 <subf_B>:
+ 372: 17800001.*
+ 373: 17800000.*
+ 374: 17a00000.*
+ 375: 17c00005.*
+ 376: 17e01600.*
+
+00000377 <subf_S>:
+ 377: 26800102.*
+ 378: 17800001.*
+ 379: 26a00001.*
+ 37a: 26c00100.*
+ 37b: 17c00001.*
+ 37c: 26e00100.*
+
+0000037d <subf3_S>:
+ 37d: 26800102.*
+ 37e: 26800001.*
+ 37f: 26a00001.*
+ 380: 26c00100.*
+ 381: 26c00000.*
+ 382: 26e00100.*
+
+00000383 <subf_stf_Q>:
+ 383: ea010100.*
+ 384: ea010100.*
+
+00000385 <subf3_stf_Q>:
+ 385: ea010100.*
+ 386: ea010100.*
+
+00000387 <subi_A>:
+ 387: 18080009.*
+ 388: 18080008.*
+ 389: 18280000.*
+ 38a: 18480005.*
+ 38b: 1868fffb.*
+
+0000038c <subi_T>:
+ 38c: 2708090a.*
+ 38d: 18080009.*
+ 38e: 27280009.*
+ 38f: 27480900.*
+ 390: 18480001.*
+ 391: 27680001.*
+
+00000392 <subi3_T>:
+ 392: 2708090a.*
+ 393: 27080809.*
+ 394: 27280009.*
+ 395: 27480900.*
+ 396: 27480800.*
+ 397: 27680001.*
+
+00000398 <subi_sti_Q>:
+ 398: ec010100.*
+ 399: ec010100.*
+
+0000039a <subi3_sti_Q>:
+ 39a: ec010100.*
+ 39b: ec010100.*
+
+0000039c <subrb_A>:
+ 39c: 18880009.*
+ 39d: 18880008.*
+ 39e: 18a80000.*
+ 39f: 18c80005.*
+ 3a0: 18e8fffb.*
+
+000003a1 <subrf_B>:
+ 3a1: 19000001.*
+ 3a2: 19000000.*
+ 3a3: 19200000.*
+ 3a4: 19400005.*
+ 3a5: 19601600.*
+
+000003a6 <subri_A>:
+ 3a6: 19880009.*
+ 3a7: 19880008.*
+ 3a8: 19a80000.*
+ 3a9: 19c80005.*
+ 3aa: 19e8fffb.*
+
+000003ab <swi_Z>:
+ 3ab: 66000000.*
+
+000003ac <trap_Z>:
+ 3ac: 7401002a.*
+ 3ad: 7400002a.*
+
+000003ae <tstb_AU>:
+ 3ae: 1a080009.*
+ 3af: 1a080008.*
+ 3b0: 1a280000.*
+ 3b1: 1a480005.*
+ 3b2: 1a680005.*
+
+000003b3 <tstb_T2C>:
+ 3b3: 1a09000a.*
+ 3b4: 27a00009.*
+ 3b5: 1a490001.*
+ 3b6: 27e00001.*
+
+000003b7 <tstb3_T2C>:
+ 3b7: 2780090a.*
+ 3b8: 27a00009.*
+ 3b9: 27c00900.*
+ 3ba: 27e00001.*
+
+000003bb <xor_AU>:
+ 3bb: 1a880009.*
+ 3bc: 1a880008.*
+ 3bd: 1aa80000.*
+ 3be: 1ac80005.*
+ 3bf: 1ae80005.*
+
+000003c0 <xor_TC>:
+ 3c0: 2808090a.*
+ 3c1: 1a880009.*
+ 3c2: 28280009.*
+ 3c3: 28480900.*
+ 3c4: 1ac80001.*
+ 3c5: 28680001.*
+
+000003c6 <xor3_TC>:
+ 3c6: 2808090a.*
+ 3c7: 28080809.*
+ 3c8: 28280009.*
+ 3c9: 28480900.*
+ 3ca: 28480800.*
+ 3cb: 28680001.*
+
+000003cc <xor_sti_QC>:
+ 3cc: ee090100.*
+ 3cd: ee010100.*
+ 3ce: ee010100.*
+ 3cf: ee090100.*
+ 3d0: ee010100.*
+ 3d1: ee010100.*
+
+000003d2 <xor3_sti_QC>:
+ 3d2: ee090100.*
+ 3d3: ee010100.*
+ 3d4: ee010100.*
+ 3d5: ee090100.*
+ 3d6: ee010100.*
+ 3d7: ee010100.*
--- /dev/null
+#as: -m40 --defsym TEST_C4X=1
+#objdump: -d -z
+#name: c4x opcodes
+#source: opcodes.s
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <absf_B>:
+ 0: 00000001.*
+ 1: 00000000.*
+ 2: 00200000.*
+ 3: 00400005.*
+ 4: 00601600.*
+
+00000005 <absf_stf_P>:
+ 5: c8010100.*
+ 6: c8010100.*
+
+00000007 <absi_A>:
+ 7: 00880009.*
+ 8: 00880008.*
+ 9: 00a80000.*
+ a: 00c80005.*
+ b: 00e8fffb.*
+
+0000000c <absi_sti_P>:
+ c: ca010100.*
+ d: ca010100.*
+
+0000000e <addc_A>:
+ e: 01080009.*
+ f: 01080008.*
+ 10: 01280000.*
+ 11: 01480005.*
+ 12: 0168fffb.*
+
+00000013 <addc_TC>:
+ 13: 2008090a.*
+ 14: 01080009.*
+ 15: 20280009.*
+ 16: 20480900.*
+ 17: 01480001.*
+ 18: 20680001.*
+ 19: 30080905.*
+ 1a: 01680005.*
+ 1b: 300809fb.*
+ 1c: 30280928.*
+ 1d: 01480005.*
+ 1e: 30280928.*
+ 1f: 30482805.*
+ 20: 304828fb.*
+ 21: 30682928.*
+
+00000022 <addc3_TC>:
+ 22: 2008090a.*
+ 23: 20080809.*
+ 24: 20280009.*
+ 25: 20480900.*
+ 26: 20480800.*
+ 27: 20680001.*
+ 28: 300809fb.*
+ 29: 300808fb.*
+ 2a: 300809fb.*
+ 2b: 30280928.*
+ 2c: 30280828.*
+ 2d: 30280928.*
+ 2e: 304828fb.*
+ 2f: 304828fb.*
+ 30: 30682928.*
+
+00000031 <addf_B>:
+ 31: 01800001.*
+ 32: 01800000.*
+ 33: 01a00000.*
+ 34: 01c00005.*
+ 35: 01e01600.*
+
+00000036 <addf_SC>:
+ 36: 20800102.*
+ 37: 01800001.*
+ 38: 20a00001.*
+ 39: 20c00100.*
+ 3a: 01c00001.*
+ 3b: 20e00100.*
+ 3c: 30a00128.*
+ 3d: 01c00005.*
+ 3e: 30a00128.*
+ 3f: 30e02928.*
+
+00000040 <addf3_SC>:
+ 40: 20800102.*
+ 41: 20800001.*
+ 42: 20a00001.*
+ 43: 20c00100.*
+ 44: 20c00000.*
+ 45: 20e00100.*
+ 46: 30a00128.*
+ 47: 30a00028.*
+ 48: 30a00128.*
+ 49: 30e02928.*
+
+0000004a <addf_stf_QC>:
+ 4a: cc090100.*
+ 4b: cc010100.*
+ 4c: cc010100.*
+ 4d: cc090100.*
+ 4e: cc010100.*
+ 4f: cc010100.*
+
+00000050 <addf3_stf_QC>:
+ 50: cc090100.*
+ 51: cc010100.*
+ 52: cc010100.*
+ 53: cc090100.*
+ 54: cc010100.*
+ 55: cc010100.*
+
+00000056 <addi_A>:
+ 56: 02080009.*
+ 57: 02080008.*
+ 58: 02280000.*
+ 59: 02480005.*
+ 5a: 0268fffb.*
+
+0000005b <addi_TC>:
+ 5b: 2108090a.*
+ 5c: 02080009.*
+ 5d: 21280009.*
+ 5e: 21480900.*
+ 5f: 02480001.*
+ 60: 21680001.*
+ 61: 31080905.*
+ 62: 02680005.*
+ 63: 310809fb.*
+ 64: 31280928.*
+ 65: 02480005.*
+ 66: 31280928.*
+ 67: 31482805.*
+ 68: 314828fb.*
+ 69: 31682928.*
+
+0000006a <addi3_TC>:
+ 6a: 2108090a.*
+ 6b: 21080809.*
+ 6c: 21280009.*
+ 6d: 21480900.*
+ 6e: 21480800.*
+ 6f: 21680001.*
+ 70: 310809fb.*
+ 71: 310808fb.*
+ 72: 310809fb.*
+ 73: 31280928.*
+ 74: 31280828.*
+ 75: 31280928.*
+ 76: 314828fb.*
+ 77: 314828fb.*
+ 78: 31682928.*
+
+00000079 <addi_sti_QC>:
+ 79: ce090100.*
+ 7a: ce010100.*
+ 7b: ce010100.*
+ 7c: ce090100.*
+ 7d: ce010100.*
+ 7e: ce010100.*
+
+0000007f <addi3_sti_QC>:
+ 7f: ce090100.*
+ 80: ce010100.*
+ 81: ce010100.*
+ 82: ce090100.*
+ 83: ce010100.*
+ 84: ce010100.*
+
+00000085 <and_AU>:
+ 85: 02880009.*
+ 86: 02880008.*
+ 87: 02a80000.*
+ 88: 02c80005.*
+ 89: 02e80005.*
+
+0000008a <and_TC>:
+ 8a: 2188090a.*
+ 8b: 02880009.*
+ 8c: 21a80009.*
+ 8d: 21c80900.*
+ 8e: 02c80001.*
+ 8f: 21e80001.*
+ 90: 31880905.*
+ 91: 02e80005.*
+ 92: 318809fb.*
+ 93: 31a80928.*
+ 94: 02c80005.*
+ 95: 31a80928.*
+ 96: 31c82805.*
+ 97: 31c828fb.*
+ 98: 31e82928.*
+
+00000099 <and3_TC>:
+ 99: 2188090a.*
+ 9a: 21880809.*
+ 9b: 21a80009.*
+ 9c: 21c80900.*
+ 9d: 21c80800.*
+ 9e: 21e80001.*
+ 9f: 318809fb.*
+ a0: 318808fb.*
+ a1: 318809fb.*
+ a2: 31a80928.*
+ a3: 31a80828.*
+ a4: 31a80928.*
+ a5: 31c828fb.*
+ a6: 31c828fb.*
+ a7: 31e82928.*
+
+000000a8 <and_sti_QC>:
+ a8: d0090100.*
+ a9: d0010100.*
+ aa: d0010100.*
+ ab: d0090100.*
+ ac: d0010100.*
+ ad: d0010100.*
+
+000000ae <and3_sti_QC>:
+ ae: d0090100.*
+ af: d0010100.*
+ b0: d0010100.*
+ b1: d0090100.*
+ b2: d0010100.*
+ b3: d0010100.*
+
+000000b4 <andn_AU>:
+ b4: 03080009.*
+ b5: 03080008.*
+ b6: 03280000.*
+ b7: 03480005.*
+ b8: 03680005.*
+
+000000b9 <andn_T>:
+ b9: 2208090a.*
+ ba: 03080009.*
+ bb: 22280009.*
+ bc: 22480900.*
+ bd: 03480001.*
+ be: 22680001.*
+ bf: 32080905.*
+ c0: 03680005.*
+ c1: 32280928.*
+ c2: 03480005.*
+ c3: 32482805.*
+ c4: 32682928.*
+
+000000c5 <andn3_T>:
+ c5: 2208090a.*
+ c6: 22080809.*
+ c7: 22280009.*
+ c8: 22480900.*
+ c9: 22480800.*
+ ca: 22680001.*
+ cb: 320809fb.*
+ cc: 320808fb.*
+ cd: 32280928.*
+ ce: 32280828.*
+ cf: 324828fb.*
+ d0: 32682928.*
+
+000000d1 <ash_A>:
+ d1: 03880009.*
+ d2: 03880008.*
+ d3: 03a80000.*
+ d4: 03c80005.*
+ d5: 03e8fffb.*
+
+000000d6 <ash_T>:
+ d6: 2288090a.*
+ d7: 03880009.*
+ d8: 22a80009.*
+ d9: 22c80900.*
+ da: 03c80001.*
+ db: 22e80001.*
+ dc: 32880905.*
+ dd: 03e80005.*
+ de: 32a80928.*
+ df: 03c80005.*
+ e0: 32c82805.*
+ e1: 32e82928.*
+
+000000e2 <ash3_T>:
+ e2: 2288090a.*
+ e3: 22880809.*
+ e4: 22a80009.*
+ e5: 22c80900.*
+ e6: 22c80800.*
+ e7: 22e80001.*
+ e8: 328809fb.*
+ e9: 328808fb.*
+ ea: 32a80928.*
+ eb: 32a80828.*
+ ec: 32c828fb.*
+ ed: 32e82928.*
+
+000000ee <ash_sti_Q>:
+ ee: d2010100.*
+ ef: d2010100.*
+
+000000f0 <ash3_sti_Q>:
+ f0: d2010100.*
+ f1: d2010100.*
+
+000000f2 <bC_J>:
+ f2: 68010000.*
+ f3: 6a01ff0c.*
+
+000000f4 <b_J>:
+ f4: 68000000.*
+ f5: 6a00ff0a.*
+
+000000f6 <bCd_J>:
+ f6: 68210000.*
+ f7: 6a21ff06.*
+
+000000f8 <bd_J>:
+ f8: 68200000.*
+ f9: 6a20ff04.*
+
+000000fa <br_I>:
+ fa: 60ffff05.*
+
+000000fb <brd_I>:
+ fb: 61ffff02.*
+
+000000fc <call_I>:
+ fc: 62ffff03.*
+
+000000fd <call_JS>:
+ fd: 70010000.*
+ fe: 7201ff01.*
+
+000000ff <cmpf_B>:
+ ff: 04000001.*
+ 100: 04000000.*
+ 101: 04200000.*
+ 102: 04400005.*
+ 103: 04601600.*
+
+00000104 <cmpf_S2>:
+ 104: 04010002.*
+ 105: 23200001.*
+ 106: 04410001.*
+ 107: 23600100.*
+ 108: 04410005.*
+ 109: 33602928.*
+
+0000010a <cmpf3_S2>:
+ 10a: 23000102.*
+ 10b: 23200001.*
+ 10c: 23400100.*
+ 10d: 23600100.*
+ 10e: 33200128.*
+ 10f: 33602928.*
+
+00000110 <cmpi_A>:
+ 110: 04880009.*
+ 111: 04880008.*
+ 112: 04a80000.*
+ 113: 04c80005.*
+ 114: 04e8fffb.*
+
+00000115 <cmpi_T2>:
+ 115: 0489000a.*
+ 116: 23a00009.*
+ 117: 04c90001.*
+ 118: 23e00001.*
+ 119: 04e9fffb.*
+ 11a: 04c90005.*
+ 11b: 33c028fb.*
+ 11c: 33e02928.*
+
+0000011d <cmpi3_T2>:
+ 11d: 2380090a.*
+ 11e: 23a00009.*
+ 11f: 23c00900.*
+ 120: 23e00001.*
+ 121: 338009fb.*
+ 122: 33a00928.*
+ 123: 33c028fb.*
+ 124: 33e02928.*
+
+00000125 <dbC_D>:
+ 125: 6c010000.*
+ 126: 6e01fed9.*
+
+00000127 <db_D>:
+ 127: 6c000000.*
+ 128: 6e00fed7.*
+
+00000129 <dbCd_D>:
+ 129: 6c210000.*
+ 12a: 6e21fed3.*
+
+0000012b <dbd_D>:
+ 12b: 6c200000.*
+ 12c: 6e20fed1.*
+
+0000012d <fix_AF>:
+ 12d: 05000001.*
+ 12e: 05000000.*
+ 12f: 05280000.*
+ 130: 05480005.*
+ 131: 05681600.*
+
+00000132 <fix_sti_P>:
+ 132: d4010100.*
+ 133: d4010100.*
+
+00000134 <float_BI>:
+ 134: 05800009.*
+ 135: 05800000.*
+ 136: 05a00000.*
+ 137: 05c00005.*
+ 138: 05e0fffb.*
+
+00000139 <float_stf_P>:
+ 139: d6010100.*
+ 13a: d6010100.*
+
+0000013b <iack_Z>:
+ 13b: 1b200000.*
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+
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+
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+ 3d4: 0fa00000.*
+
+000003d5 <reti_Z>:
+ 3d5: 78010000.*
+ 3d6: 78000000.*
+
+000003d7 <rets_Z>:
+ 3d7: 78810000.*
+ 3d8: 78800000.*
+
+000003d9 <rnd_B>:
+ 3d9: 11000001.*
+ 3da: 11000000.*
+ 3db: 11200000.*
+ 3dc: 11400005.*
+ 3dd: 11601600.*
+
+000003de <rol_R>:
+ 3de: 11e80001.*
+
+000003df <rolc_R>:
+ 3df: 12680001.*
+
+000003e0 <ror_R>:
+ 3e0: 12e8ffff.*
+
+000003e1 <rorc_R>:
+ 3e1: 1368ffff.*
+
+000003e2 <rptb_I2>:
+ 3e2: 64fffc1d.*
+
+000003e3 <rpts_A3>:
+ 3e3: 139b0009.*
+ 3e4: 13bb0000.*
+ 3e5: 13db0005.*
+ 3e6: 13fb0005.*
+
+000003e7 <sigi_Z>:
+ 3e7: 16000000.*
+
+000003e8 <stf_B7>:
+ 3e8: 14200000.*
+ 3e9: 14400005.*
+
+000003ea <stf_LS>:
+ 3ea: c0010100.*
+ 3eb: c0010100.*
+ 3ec: c0010100.*
+
+000003ed <stfi_B7>:
+ 3ed: 14a00000.*
+ 3ee: 14c00005.*
+
+000003ef <sti_A7>:
+ 3ef: 15280000.*
+ 3f0: 15480005.*
+
+000003f1 <sti_LS>:
+ 3f1: c2010100.*
+ 3f2: c2010100.*
+ 3f3: c2010100.*
+
+000003f4 <stii_A7>:
+ 3f4: 15a80000.*
+ 3f5: 15c80005.*
+
+000003f6 <subb_A>:
+ 3f6: 16880009.*
+ 3f7: 16880008.*
+ 3f8: 16a80000.*
+ 3f9: 16c80005.*
+ 3fa: 16e8fffb.*
+
+000003fb <subb_T>:
+ 3fb: 2608090a.*
+ 3fc: 16880009.*
+ 3fd: 26280009.*
+ 3fe: 26480900.*
+ 3ff: 16c80001.*
+ 400: 26680001.*
+ 401: 36080905.*
+ 402: 16e80005.*
+ 403: 36280928.*
+ 404: 16c80005.*
+ 405: 36482805.*
+ 406: 36682928.*
+
+00000407 <subb3_T>:
+ 407: 2608090a.*
+ 408: 26080809.*
+ 409: 26280009.*
+ 40a: 26480900.*
+ 40b: 26480800.*
+ 40c: 26680001.*
+ 40d: 360809fb.*
+ 40e: 360808fb.*
+ 40f: 36280928.*
+ 410: 36280828.*
+ 411: 364828fb.*
+ 412: 36682928.*
+
+00000413 <subc_A>:
+ 413: 17080009.*
+ 414: 17080008.*
+ 415: 17280000.*
+ 416: 17480005.*
+ 417: 1768fffb.*
+
+00000418 <subf_B>:
+ 418: 17800001.*
+ 419: 17800000.*
+ 41a: 17a00000.*
+ 41b: 17c00005.*
+ 41c: 17e01600.*
+
+0000041d <subf_S>:
+ 41d: 26800102.*
+ 41e: 17800001.*
+ 41f: 26a00001.*
+ 420: 26c00100.*
+ 421: 17c00001.*
+ 422: 26e00100.*
+ 423: 36a00128.*
+ 424: 17c00005.*
+ 425: 36e02928.*
+
+00000426 <subf3_S>:
+ 426: 26800102.*
+ 427: 26800001.*
+ 428: 26a00001.*
+ 429: 26c00100.*
+ 42a: 26c00000.*
+ 42b: 26e00100.*
+ 42c: 36a00128.*
+ 42d: 36a00028.*
+ 42e: 36e02928.*
+
+0000042f <subf_stf_Q>:
+ 42f: ea010100.*
+ 430: ea010100.*
+
+00000431 <subf3_stf_Q>:
+ 431: ea010100.*
+ 432: ea010100.*
+
+00000433 <subi_A>:
+ 433: 18080009.*
+ 434: 18080008.*
+ 435: 18280000.*
+ 436: 18480005.*
+ 437: 1868fffb.*
+
+00000438 <subi_T>:
+ 438: 2708090a.*
+ 439: 18080009.*
+ 43a: 27280009.*
+ 43b: 27480900.*
+ 43c: 18480001.*
+ 43d: 27680001.*
+ 43e: 37080905.*
+ 43f: 18680005.*
+ 440: 37280928.*
+ 441: 18480005.*
+ 442: 37482805.*
+ 443: 37682928.*
+
+00000444 <subi3_T>:
+ 444: 2708090a.*
+ 445: 27080809.*
+ 446: 27280009.*
+ 447: 27480900.*
+ 448: 27480800.*
+ 449: 27680001.*
+ 44a: 370809fb.*
+ 44b: 370808fb.*
+ 44c: 37280928.*
+ 44d: 37280828.*
+ 44e: 374828fb.*
+ 44f: 37682928.*
+
+00000450 <subi_sti_Q>:
+ 450: ec010100.*
+ 451: ec010100.*
+
+00000452 <subi3_sti_Q>:
+ 452: ec010100.*
+ 453: ec010100.*
+
+00000454 <subrb_A>:
+ 454: 18880009.*
+ 455: 18880008.*
+ 456: 18a80000.*
+ 457: 18c80005.*
+ 458: 18e8fffb.*
+
+00000459 <subrf_B>:
+ 459: 19000001.*
+ 45a: 19000000.*
+ 45b: 19200000.*
+ 45c: 19400005.*
+ 45d: 19601600.*
+
+0000045e <subri_A>:
+ 45e: 19880009.*
+ 45f: 19880008.*
+ 460: 19a80000.*
+ 461: 19c80005.*
+ 462: 19e8fffb.*
+
+00000463 <swi_Z>:
+ 463: 66000000.*
+
+00000464 <trap_Z>:
+ 464: 7401000a.*
+ 465: 7400000a.*
+
+00000466 <tstb_AU>:
+ 466: 1a080009.*
+ 467: 1a080008.*
+ 468: 1a280000.*
+ 469: 1a480005.*
+ 46a: 1a680005.*
+
+0000046b <tstb_T2C>:
+ 46b: 1a09000a.*
+ 46c: 27a00009.*
+ 46d: 1a490001.*
+ 46e: 27e00001.*
+ 46f: 1a690005.*
+ 470: 378009fb.*
+ 471: 1a490005.*
+ 472: 37a00928.*
+ 473: 37c02805.*
+ 474: 37c028fb.*
+ 475: 37e02928.*
+
+00000476 <tstb3_T2C>:
+ 476: 2780090a.*
+ 477: 27a00009.*
+ 478: 27c00900.*
+ 479: 27e00001.*
+ 47a: 378009fb.*
+ 47b: 378009fb.*
+ 47c: 37a00928.*
+ 47d: 37a00928.*
+ 47e: 37c028fb.*
+ 47f: 37c028fb.*
+ 480: 37e02928.*
+
+00000481 <xor_AU>:
+ 481: 1a880009.*
+ 482: 1a880008.*
+ 483: 1aa80000.*
+ 484: 1ac80005.*
+ 485: 1ae80005.*
+
+00000486 <xor_TC>:
+ 486: 2808090a.*
+ 487: 1a880009.*
+ 488: 28280009.*
+ 489: 28480900.*
+ 48a: 1ac80001.*
+ 48b: 28680001.*
+ 48c: 38080905.*
+ 48d: 1ae80005.*
+ 48e: 380809fb.*
+ 48f: 38280928.*
+ 490: 1ac80005.*
+ 491: 38280928.*
+ 492: 38482805.*
+ 493: 384828fb.*
+ 494: 38682928.*
+
+00000495 <xor3_TC>:
+ 495: 2808090a.*
+ 496: 28080809.*
+ 497: 28280009.*
+ 498: 28480900.*
+ 499: 28480800.*
+ 49a: 28680001.*
+ 49b: 380809fb.*
+ 49c: 380808fb.*
+ 49d: 380809fb.*
+ 49e: 38280928.*
+ 49f: 38280828.*
+ 4a0: 38280928.*
+ 4a1: 384828fb.*
+ 4a2: 384828fb.*
+ 4a3: 38682928.*
+
+000004a4 <xor_sti_QC>:
+ 4a4: ee090100.*
+ 4a5: ee010100.*
+ 4a6: ee010100.*
+ 4a7: ee090100.*
+ 4a8: ee010100.*
+ 4a9: ee010100.*
+
+000004aa <xor3_sti_QC>:
+ 4aa: ee090100.*
+ 4ab: ee010100.*
+ 4ac: ee010100.*
+ 4ad: ee090100.*
+ 4ae: ee010100.*
+ 4af: ee010100.*
+
+000004b0 <bCaf_J>:
+ 4b0: 68a10000.*
+ 4b1: 6aa1fb4c.*
+
+000004b2 <baf_J>:
+ 4b2: 68a00000.*
+ 4b3: 6aa0fb4a.*
+
+000004b4 <bCat_J>:
+ 4b4: 68610000.*
+ 4b5: 6a61fb48.*
+
+000004b6 <bat_J>:
+ 4b6: 68600000.*
+ 4b7: 6a60fb46.*
+
+000004b8 <frieee_B6>:
+ 4b8: 1c200000.*
+ 4b9: 1c400005.*
+
+000004ba <frieee_stf_P>:
+ 4ba: f2010100.*
+ 4bb: f2010100.*
+
+000004bc <laj_I>:
+ 4bc: 63fffb41.*
+
+000004bd <laj_JS>:
+ 4bd: 70210000.*
+ 4be: 7221fb3f.*
+
+000004bf <lat_Z>:
+ 4bf: 7481000a.*
+
+000004c0 <lb0_A>:
+ 4c0: b0080009.*
+ 4c1: b0080008.*
+ 4c2: b0280000.*
+ 4c3: b0480005.*
+ 4c4: b068fffb.*
+
+000004c5 <lb1_A>:
+ 4c5: b0880009.*
+ 4c6: b0880008.*
+ 4c7: b0a80000.*
+ 4c8: b0c80005.*
+ 4c9: b0e8fffb.*
+
+000004ca <lb2_A>:
+ 4ca: b1080009.*
+ 4cb: b1080008.*
+ 4cc: b1280000.*
+ 4cd: b1480005.*
+ 4ce: b168fffb.*
+
+000004cf <lb3_A>:
+ 4cf: b1880009.*
+ 4d0: b1880008.*
+ 4d1: b1a80000.*
+ 4d2: b1c80005.*
+ 4d3: b1e8fffb.*
+
+000004d4 <lbu0_AU>:
+ 4d4: b2080009.*
+ 4d5: b2080008.*
+ 4d6: b2280000.*
+ 4d7: b2480005.*
+ 4d8: b2680005.*
+
+000004d9 <lbu1_AU>:
+ 4d9: b2880009.*
+ 4da: b2880008.*
+ 4db: b2a80000.*
+ 4dc: b2c80005.*
+ 4dd: b2e80005.*
+
+000004de <lbu2_AU>:
+ 4de: b3080009.*
+ 4df: b3080008.*
+ 4e0: b3280000.*
+ 4e1: b3480005.*
+ 4e2: b3680005.*
+
+000004e3 <lbu3_AU>:
+ 4e3: b3880009.*
+ 4e4: b3880008.*
+ 4e5: b3a80000.*
+ 4e6: b3c80005.*
+ 4e7: b3e80005.*
+
+000004e8 <lda_AY>:
+ 4e8: 1e880009.*
+ 4e9: 1ea80000.*
+ 4ea: 1ec80005.*
+ 4eb: 1ee8fffb.*
+
+000004ec <ldep_Z>:
+ 4ec: 76080000.*
+
+000004ed <ldhi_Z>:
+ 4ed: 1fe00023.*
+ 4ee: 1fe00000.*
+
+000004ef <ldpe_Z>:
+ 4ef: 76800008.*
+
+000004f0 <ldpk_Z>:
+ 4f0: 1f700000.*
+
+000004f1 <lh0_A>:
+ 4f1: ba080009.*
+ 4f2: ba080008.*
+ 4f3: ba280000.*
+ 4f4: ba480005.*
+ 4f5: ba68fffb.*
+
+000004f6 <lh1_A>:
+ 4f6: ba880009.*
+ 4f7: ba880008.*
+ 4f8: baa80000.*
+ 4f9: bac80005.*
+ 4fa: bae8fffb.*
+
+000004fb <lhu0_AU>:
+ 4fb: bb080009.*
+ 4fc: bb080008.*
+ 4fd: bb280000.*
+ 4fe: bb480005.*
+ 4ff: bb680005.*
+
+00000500 <lhu1_AU>:
+ 500: bb880009.*
+ 501: bb880008.*
+ 502: bba80000.*
+ 503: bbc80005.*
+ 504: bbe80005.*
+
+00000505 <lwl0_A>:
+ 505: b4080009.*
+ 506: b4080008.*
+ 507: b4280000.*
+ 508: b4480005.*
+ 509: b468fffb.*
+
+0000050a <lwl1_A>:
+ 50a: b4880009.*
+ 50b: b4880008.*
+ 50c: b4a80000.*
+ 50d: b4c80005.*
+ 50e: b4e8fffb.*
+
+0000050f <lwl2_A>:
+ 50f: b5080009.*
+ 510: b5080008.*
+ 511: b5280000.*
+ 512: b5480005.*
+ 513: b568fffb.*
+
+00000514 <lwl3_A>:
+ 514: b5880009.*
+ 515: b5880008.*
+ 516: b5a80000.*
+ 517: b5c80005.*
+ 518: b5e8fffb.*
+
+00000519 <lwr0_A>:
+ 519: b6080009.*
+ 51a: b6080008.*
+ 51b: b6280000.*
+ 51c: b6480005.*
+ 51d: b668fffb.*
+
+0000051e <lwr1_A>:
+ 51e: b6880009.*
+ 51f: b6880008.*
+ 520: b6a80000.*
+ 521: b6c80005.*
+ 522: b6e8fffb.*
+
+00000523 <lwr2_A>:
+ 523: b7080009.*
+ 524: b7080008.*
+ 525: b7280000.*
+ 526: b7480005.*
+ 527: b768fffb.*
+
+00000528 <lwr3_A>:
+ 528: b7880009.*
+ 529: b7880008.*
+ 52a: b7a80000.*
+ 52b: b7c80005.*
+ 52c: b7e8fffb.*
+
+0000052d <mb0_A>:
+ 52d: b8080009.*
+ 52e: b8080008.*
+ 52f: b8280000.*
+ 530: b8480005.*
+ 531: b868fffb.*
+
+00000532 <mb1_A>:
+ 532: b8880009.*
+ 533: b8880008.*
+ 534: b8a80000.*
+ 535: b8c80005.*
+ 536: b8e8fffb.*
+
+00000537 <mb2_A>:
+ 537: b9080009.*
+ 538: b9080008.*
+ 539: b9280000.*
+ 53a: b9480005.*
+ 53b: b968fffb.*
+
+0000053c <mb3_A>:
+ 53c: b9880009.*
+ 53d: b9880008.*
+ 53e: b9a80000.*
+ 53f: b9c80005.*
+ 540: b9e8fffb.*
+
+00000541 <mh0_A>:
+ 541: bc080009.*
+ 542: bc080008.*
+ 543: bc280000.*
+ 544: bc480005.*
+ 545: bc68fffb.*
+
+00000546 <mh1_A>:
+ 546: bc880009.*
+ 547: bc880008.*
+ 548: bca80000.*
+ 549: bcc80005.*
+ 54a: bce8fffb.*
+
+0000054b <mh2_A>:
+ 54b: bd080009.*
+ 54c: bd080008.*
+ 54d: bd280000.*
+ 54e: bd480005.*
+ 54f: bd68fffb.*
+
+00000550 <mh3_A>:
+ 550: bd880009.*
+ 551: bd880008.*
+ 552: bda80000.*
+ 553: bdc80005.*
+ 554: bde8fffb.*
+
+00000555 <mpyshi_A>:
+ 555: 1d880009.*
+ 556: 1d880008.*
+ 557: 1da80000.*
+ 558: 1dc80005.*
+ 559: 1de8fffb.*
+
+0000055a <mpyshi_TC>:
+ 55a: 2888090a.*
+ 55b: 1d880009.*
+ 55c: 28a80009.*
+ 55d: 28c80900.*
+ 55e: 1dc80001.*
+ 55f: 28e80001.*
+ 560: 38880905.*
+ 561: 1de80005.*
+ 562: 388809fb.*
+ 563: 38a80928.*
+ 564: 1dc80005.*
+ 565: 38a80928.*
+ 566: 38c82805.*
+ 567: 38c828fb.*
+ 568: 38e82928.*
+
+00000569 <mpyshi3_TC>:
+ 569: 2888090a.*
+ 56a: 28880809.*
+ 56b: 28a80009.*
+ 56c: 28c80900.*
+ 56d: 28c80800.*
+ 56e: 28e80001.*
+ 56f: 388809fb.*
+ 570: 388808fb.*
+ 571: 388809fb.*
+ 572: 38a80928.*
+ 573: 38a80828.*
+ 574: 38a80928.*
+ 575: 38c828fb.*
+ 576: 38c828fb.*
+ 577: 38e82928.*
+
+00000578 <mpyuhi_A>:
+ 578: 1e080009.*
+ 579: 1e080008.*
+ 57a: 1e280000.*
+ 57b: 1e480005.*
+ 57c: 1e68fffb.*
+
+0000057d <mpyuhi_TC>:
+ 57d: 2908090a.*
+ 57e: 1e080009.*
+ 57f: 29280009.*
+ 580: 29480900.*
+ 581: 1e480001.*
+ 582: 29680001.*
+ 583: 39080905.*
+ 584: 1e680005.*
+ 585: 390809fb.*
+ 586: 39280928.*
+ 587: 1e480005.*
+ 588: 39280928.*
+ 589: 39482805.*
+ 58a: 394828fb.*
+ 58b: 39682928.*
+
+0000058c <mpyuhi3_TC>:
+ 58c: 2908090a.*
+ 58d: 29080809.*
+ 58e: 29280009.*
+ 58f: 29480900.*
+ 590: 29480800.*
+ 591: 29680001.*
+ 592: 390809fb.*
+ 593: 390808fb.*
+ 594: 390809fb.*
+ 595: 39280928.*
+ 596: 39280828.*
+ 597: 39280928.*
+ 598: 394828fb.*
+ 599: 394828fb.*
+ 59a: 39682928.*
+
+0000059b <rcpf_BA>:
+ 59b: 1d000009.*
+ 59c: 1d000000.*
+ 59d: 1d200000.*
+ 59e: 1d400005.*
+ 59f: 1d601600.*
+
+000005a0 <retid_Z>:
+ 5a0: 78210000.*
+ 5a1: 78200000.*
+
+000005a2 <rptb2_I2>:
+ 5a2: 79000008.*
+
+000005a3 <rptbd_I2>:
+ 5a3: 65fffa5a.*
+ 5a4: 79800008.*
+
+000005a5 <rsqrf_B>:
+ 5a5: 1c800001.*
+ 5a6: 1c800000.*
+ 5a7: 1ca00000.*
+ 5a8: 1cc00005.*
+ 5a9: 1ce01600.*
+
+000005aa <sigi_A6>:
+ 5aa: 16280000.*
+ 5ab: 16480005.*
+
+000005ac <sti2_A7>:
+ 5ac: 151b0000.*
+ 5ad: 157b0005.*
+
+000005ae <stik_Z>:
+ 5ae: 151b0000.*
+ 5af: 157b0005.*
+
+000005b0 <toieee_B>:
+ 5b0: 1b800001.*
+ 5b1: 1b800000.*
+ 5b2: 1ba00000.*
+ 5b3: 1bc00005.*
+ 5b4: 1be01600.*
+
+000005b5 <toieee_stf_P>:
+ 5b5: f0010100.*
+ 5b6: f0010100.*
--- /dev/null
+#!/bin/sh
+
+echo "Rebuilding opcodes.s from allopcodes.S"
+cat <<EOF >opcodes.s
+; File is autogenerated from allopcodes.S - do not edit
+; Please use ./rebuild.sh to rebuild this file
+
+EOF
+
+cpp -P allopcodes.S >>opcodes.s
--- /dev/null
+ ;; test all register names c3x
+ .text
+ ;; Test the base names
+ .ifdef TEST_ALL
+start: ldi R0,R0
+ ldi R0,R1
+ ldi R0,R2
+ ldi R0,R3
+ ldi R0,R4
+ ldi R0,R5
+ ldi R0,R6
+ ldi R0,R7
+ ldi R0,AR0
+ ldi R0,AR1
+ ldi R0,AR2
+ ldi R0,AR3
+ ldi R0,AR4
+ ldi R0,AR5
+ ldi R0,AR6
+ ldi R0,AR7
+ ldi R0,DP
+ ldi R0,IR0
+ ldi R0,IR1
+ ldi R0,BK
+ ldi R0,SP
+ ldi R0,ST
+ .endif
+ .ifdef TEST_C3X
+ ldi R0,IE
+ ldi R0,IF
+ ldi R0,IOF
+ .endif
+ .ifdef TEST_C4X
+ ldi R0,DIE
+ ldi R0,IIE
+ ldi R0,IIF
+ .endif
+ .ifdef TEST_ALL
+ ldi R0,RS
+ ldi R0,RE
+ ldi R0,RC
+ .endif
+ .ifdef TEST_C4X
+ ldi R0,R8
+ ldi R0,R9
+ ldi R0,R10
+ ldi R0,R11
+ ldpe R0,IVTP
+ ldpe R0,TVTP
+ .endif
+
+ ;; Test the alternative names
+ .ifdef TEST_ALL
+ ldf F0,F0
+ ldf F0,F1
+ ldf F0,F2
+ ldf F0,F3
+ ldf F0,F4
+ ldf F0,F5
+ ldf F0,F6
+ ldf F0,F7
+ .endif
+ .ifdef TEST_C4X
+ ldf F0,F8
+ ldf F0,F9
+ ldf F0,F10
+ ldf F0,F11
+ .endif
+ .end
--- /dev/null
+#as: -m30 --defsym TEST_ALL=1 --defsym TEST_C3X=1
+#objdump: -d -z
+#name: c3x registers
+#source: registers.s
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <start>:
+ 0: 08000000.*
+ 1: 08010000.*
+ 2: 08020000.*
+ 3: 08030000.*
+ 4: 08040000.*
+ 5: 08050000.*
+ 6: 08060000.*
+ 7: 08070000.*
+ 8: 08080000.*
+ 9: 08090000.*
+ a: 080a0000.*
+ b: 080b0000.*
+ c: 080c0000.*
+ d: 080d0000.*
+ e: 080e0000.*
+ f: 080f0000.*
+ 10: 08100000.*
+ 11: 08110000.*
+ 12: 08120000.*
+ 13: 08130000.*
+ 14: 08140000.*
+ 15: 08150000.*
+ 16: 08160000.*
+ 17: 08170000.*
+ 18: 08180000.*
+ 19: 08190000.*
+ 1a: 081a0000.*
+ 1b: 081b0000.*
+ 1c: 07000000.*
+ 1d: 07010000.*
+ 1e: 07020000.*
+ 1f: 07030000.*
+ 20: 07040000.*
+ 21: 07050000.*
+ 22: 07060000.*
+ 23: 07070000.*
--- /dev/null
+#as: -m40 --defsym TEST_ALL=1 --defsym TEST_C4X=1
+#objdump: -d -z
+#name: c4x registers
+#source: registers.s
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <start>:
+ 0: 08000000.*
+ 1: 08010000.*
+ 2: 08020000.*
+ 3: 08030000.*
+ 4: 08040000.*
+ 5: 08050000.*
+ 6: 08060000.*
+ 7: 08070000.*
+ 8: 08080000.*
+ 9: 08090000.*
+ a: 080a0000.*
+ b: 080b0000.*
+ c: 080c0000.*
+ d: 080d0000.*
+ e: 080e0000.*
+ f: 080f0000.*
+ 10: 08100000.*
+ 11: 08110000.*
+ 12: 08120000.*
+ 13: 08130000.*
+ 14: 08140000.*
+ 15: 08150000.*
+ 16: 08160000.*
+ 17: 08170000.*
+ 18: 08180000.*
+ 19: 08190000.*
+ 1a: 081a0000.*
+ 1b: 081b0000.*
+ 1c: 081c0000.*
+ 1d: 081d0000.*
+ 1e: 081e0000.*
+ 1f: 081f0000.*
+ 20: 76800000.*
+ 21: 76810000.*
+ 22: 07000000.*
+ 23: 07010000.*
+ 24: 07020000.*
+ 25: 07030000.*
+ 26: 07040000.*
+ 27: 07050000.*
+ 28: 07060000.*
+ 29: 07070000.*
+ 2a: 071c0000.*
+ 2b: 071d0000.*
+ 2c: 071e0000.*
+ 2d: 071f0000.*
--- /dev/null
+
+#
+# Test x930509a -- correct assembly of differences involving forward
+# references.
+#
+proc do_930509a_tic4x {} {
+ set testname "difference between forward references (tic4x version)"
+ set x 0
+ gas_start "../all/x930509.s" "-al"
+ while 1 {
+# We need to accomodate both byte orders here.
+# If ".long" means an 8-byte value on some target someday, this test will have
+# to be fixed.
+ expect {
+ -re "^ +1 .... 00 ?00 ?00 ?00" { fail $testname; set x 1 }
+ -re "^ +1 .... 01 ?00 ?00 ?00" { pass $testname; set x 1 }
+ -re "^ +1 .... 00 ?00 ?00 ?01" { pass $testname; set x 1 }
+ -re "\[^\n\]*\n" { }
+ timeout { perror "timeout\n"; break }
+ eof { break }
+ }
+ }
+ gas_finish
+ if !$x then { fail $testname }
+}
+
+
+#
+# TI TMS320C4X tests.
+#
+if [istarget *c4x*-*-*] then {
+ do_930509a_tic4x
+
+ # Test zero-based disassemble test
+ run_dump_test "zeros"
+
+ # Test the register names on the c3x and on the c4x
+ run_dump_test "registers_c3x"
+ run_dump_test "registers_c4x"
+
+ # Make sure the c4x registers dont work on c3x
+ gas_test_error "registers.s" "-m30 --defsym TEST_C4X=1" "c4x register usage in c3x"
+
+ # Test data storage
+ run_dump_test "data"
+
+ # Test flonums
+ run_dump_test "float"
+
+ # Test all addressing modes
+ run_dump_test "addressing_c3x"
+ run_dump_test "addressing_c4x"
+
+ # Make sure the c4x addressing dont work on c3x
+ gas_test_error "addressing.s" "-m30 --defsym TEST_C4X=1" "c4x addressing usage in c3x"
+
+ # Test float instructions
+ run_dump_test "opcodes_c3x"
+ run_dump_test "opcodes_c4x"
+
+ # Make sure the c4x ops dont work on c3x
+ #gas_test_error "opcodes.s" "-m30 --defsym TEST_C4X=1" "c4x instruction usage in c3x"
+ # -- for some reason this test crashes dejagnu, hence disabled!
+}
--- /dev/null
+#objdump: -d
+#name: zero-value disassemble check
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <start>:
+ 0: 00000000.*
+ 1: 00000000.*
+ 2: 00000002.*
+ ...
+ 16: 00000001.*
+ 17: 00000001.*
+ 18: 00000002.*
+ 19: 00000000.*
+ 1a: 00000001.*
+ 1b: 00000001.*
+ 1c: 00000002.*
+ 1d: 00000000.*
+ 1e: 00000000.*
+ 1f: 00000002.*
+ 20: 00000000.*
+ 21: 00000000.*
--- /dev/null
+ .text
+start: .long 0
+ .long 0
+ .long 2
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 1
+ .long 1
+ .long 2
+ .long 0
+ .long 1
+ .long 1
+ .long 2
+ .long 0
+ .long 0
+ .long 2
+ .long 0
+ .long 0
+2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
+
+ * testsuite/ld-scripts/script.exp: Setup for tic4x testcase
+
2002-11-14 Egor Duda <deo@logos-m.ru>
* ldmain.c (main): Make runtime relocs disabled by default. Remove
} else {
set text_end 0x104
set data_end 0x1004
+ if [istarget *c4x*-*-*] then {
+ set text_end 0x101
+ set data_end 0x1001
+ }
if [istarget *c54x*-*-*] then {
set text_end 0x102
set data_end 0x1002
projects / external / binutils.git / commitdiff