int uuid_state;
uuid_t uuid;
+
+ uint32_t width, height, format;
};
#define gem_to_virtio_gpu_obj(gobj) \
container_of((gobj), struct virtio_gpu_object, base.base)
};
/* virtgpu_ioctl.c */
-#define DRM_VIRTIO_NUM_IOCTLS 12
+#define DRM_VIRTIO_NUM_IOCTLS 13
extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file);
return ret;
}
+static int virtio_gpu_brutal_hack(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_virtgpu_brutal_hack *bh = data;
+ struct drm_gem_object *gobj = NULL;
+ struct virtio_gpu_object *qobj = NULL;
+
+ printk("*** a\n");
+
+ gobj = drm_gem_object_lookup(file, bh->bo_handle);
+ if (gobj == NULL) {
+ printk("*** ENOENT\n");
+ return -ENOENT;
+ }
+
+ printk("*** b\n");
+
+ qobj = gem_to_virtio_gpu_obj(gobj);
+
+ bh->width = qobj->width;
+ bh->height = qobj->height;
+ bh->pitch = qobj->width * 4;
+ switch (qobj->format) {
+ case VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM:
+ bh->format = DRM_FORMAT_XRGB8888;
+ break;
+ case VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM:
+ bh->format = DRM_FORMAT_ARGB8888;
+ break;
+ case VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM:
+ bh->format = DRM_FORMAT_BGRX8888;
+ break;
+ case VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM:
+ bh->format = DRM_FORMAT_BGRA8888;
+ break;
+ default:
+ bh->format = 0;
+ break;
+ }
+
+ printk("*** c\n");
+ drm_gem_object_put(gobj);
+ return 0;
+}
+
struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(VIRTGPU_CONTEXT_INIT, virtio_gpu_context_init_ioctl,
DRM_RENDER_ALLOW),
+
+ DRM_IOCTL_DEF_DRV(VIRTGPU_BRUTAL_HACK, virtio_gpu_brutal_hack,
+ DRM_RENDER_ALLOW),
};
#define DRM_VIRTGPU_GET_CAPS 0x09
#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
+#define DRM_VIRTGPU_BRUTAL_HACK 0x0c
#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
__u64 ctx_set_params;
};
+struct drm_virtgpu_brutal_hack {
+ __u32 bo_handle;
+ __u32 width;
+ __u32 height;
+ __u32 pitch;
+ __u32 format;
+};
+
/*
* Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
* effect. The event size is sizeof(drm_event), since there is no additional
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \
struct drm_virtgpu_context_init)
+#define DRM_IOCTL_VIRTGPU_BRUTAL_HACK \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_BRUTAL_HACK, \
+ struct drm_virtgpu_brutal_hack)
+
#if defined(__cplusplus)
}
#endif