arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes

Add pcie dtsi nodes for two controllers found on sa8775p platform.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Link: https://lore.kernel.org/r/1689960276-29266-4-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 59eedfc..7b55cb7 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -481,8 +481,8 @@
                                 <0>,
                                 <0>,
                                 <0>,
-                                <0>,
-                                <0>,
+                                <&pcie0_phy>,
+                                <&pcie1_phy>,
                                 <0>,
                                 <0>,
                                 <0>;
@@ -2357,4 +2357,204 @@
                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
        };
+
+       pcie0: pci@1c00000{
+               compatible = "qcom,pcie-sa8775p";
+               reg = <0x0 0x01c00000 0x0 0x3000>,
+                     <0x0 0x40000000 0x0 0xf20>,
+                     <0x0 0x40000f20 0x0 0xa8>,
+                     <0x0 0x40001000 0x0 0x4000>,
+                     <0x0 0x40100000 0x0 0x100000>,
+                     <0x0 0x01c03000 0x0 0x1000>;
+               reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+               device_type = "pci";
+
+               #address-cells = <3>;
+               #size-cells = <2>;
+               ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+                        <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+               bus-range = <0x00 0xff>;
+
+               dma-coherent;
+
+               linux,pci-domain = <0>;
+               num-lanes = <2>;
+
+               interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "msi0", "msi1", "msi2", "msi3",
+                                 "msi4", "msi5", "msi6", "msi7";
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0x7>;
+               interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+               clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+                        <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                        <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                        <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                        <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+
+               clock-names = "aux",
+                             "cfg",
+                             "bus_master",
+                             "bus_slave",
+                             "slave_q2a";
+
+               assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
+               assigned-clock-rates = <19200000>;
+
+               interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+                               <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
+               interconnect-names = "pcie-mem", "cpu-pcie";
+
+               iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
+                           <0x100 &pcie_smmu 0x0001 0x1>;
+
+               resets = <&gcc GCC_PCIE_0_BCR>;
+               reset-names = "pci";
+               power-domains = <&gcc PCIE_0_GDSC>;
+
+               phys = <&pcie0_phy>;
+               phy-names = "pciephy";
+
+               status = "disabled";
+       };
+
+       pcie0_phy: phy@1c04000 {
+               compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
+               reg = <0x0 0x1c04000 0x0 0x2000>;
+
+               clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+                        <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                        <&gcc GCC_PCIE_CLKREF_EN>,
+                        <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+                        <&gcc GCC_PCIE_0_PIPE_CLK>,
+                        <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
+                        <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
+
+               clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
+                             "pipediv2", "phy_aux";
+
+               assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+               assigned-clock-rates = <100000000>;
+
+               resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+               reset-names = "phy";
+
+               #clock-cells = <0>;
+               clock-output-names = "pcie_0_pipe_clk";
+
+               #phy-cells = <0>;
+
+               status = "disabled";
+       };
+
+       pcie1: pci@1c10000{
+               compatible = "qcom,pcie-sa8775p";
+               reg = <0x0 0x01c10000 0x0 0x3000>,
+                     <0x0 0x60000000 0x0 0xf20>,
+                     <0x0 0x60000f20 0x0 0xa8>,
+                     <0x0 0x60001000 0x0 0x4000>,
+                     <0x0 0x60100000 0x0 0x100000>,
+                     <0x0 0x01c13000 0x0 0x1000>;
+               reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+               device_type = "pci";
+
+               #address-cells = <3>;
+               #size-cells = <2>;
+               ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+                        <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
+               bus-range = <0x00 0xff>;
+
+               dma-coherent;
+
+               linux,pci-domain = <1>;
+               num-lanes = <4>;
+
+               interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "msi0", "msi1", "msi2", "msi3",
+                                 "msi4", "msi5", "msi6", "msi7";
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0x7>;
+               interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+
+               clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+                        <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+                        <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+                        <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+                        <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+
+               clock-names = "aux",
+                             "cfg",
+                             "bus_master",
+                             "bus_slave",
+                             "slave_q2a";
+
+               assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+               assigned-clock-rates = <19200000>;
+
+               interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
+                               <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
+               interconnect-names = "pcie-mem", "cpu-pcie";
+
+               iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
+                           <0x100 &pcie_smmu 0x0081 0x1>;
+
+               resets = <&gcc GCC_PCIE_1_BCR>;
+               reset-names = "pci";
+               power-domains = <&gcc PCIE_1_GDSC>;
+
+               phys = <&pcie1_phy>;
+               phy-names = "pciephy";
+
+               status = "disabled";
+       };
+
+       pcie1_phy: phy@1c14000 {
+               compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
+               reg = <0x0 0x1c14000 0x0 0x4000>;
+
+               clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+                        <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+                        <&gcc GCC_PCIE_CLKREF_EN>,
+                        <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+                        <&gcc GCC_PCIE_1_PIPE_CLK>,
+                        <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
+                        <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
+
+               clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
+                             "pipediv2", "phy_aux";
+
+               assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+               assigned-clock-rates = <100000000>;
+
+               resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+               reset-names = "phy";
+
+               #clock-cells = <0>;
+               clock-output-names = "pcie_1_pipe_clk";
+
+               #phy-cells = <0>;
+
+               status = "disabled";
+       };
 };