unsigned FunctionNumber;
/// Alignment - The alignment of the function.
- unsigned LogAlignment;
+ llvm::Align Alignment;
/// ExposesReturnsTwice - True if the function calls setjmp or related
/// functions with attribute "returns twice", but doesn't have
const WinEHFuncInfo *getWinEHFuncInfo() const { return WinEHInfo; }
WinEHFuncInfo *getWinEHFuncInfo() { return WinEHInfo; }
- /// getLogAlignment - Return the alignment of the function.
- unsigned getLogAlignment() const { return LogAlignment; }
+ /// getAlignment - Return the alignment of the function.
+ llvm::Align getAlignment() const { return Alignment; }
- /// setLogAlignment - Set the alignment of the function.
- void setLogAlignment(unsigned A) { LogAlignment = A; }
+ /// setAlignment - Set the alignment of the function.
+ void setAlignment(llvm::Align A) { Alignment = A; }
- /// ensureAlignment - Make sure the function is at least 1 << A bytes aligned.
- void ensureLogAlignment(unsigned A) {
- if (LogAlignment < A)
- LogAlignment = A;
+ /// ensureAlignment - Make sure the function is at least A bytes aligned.
+ void ensureAlignment(llvm::Align A) {
+ if (Alignment < A)
+ Alignment = A;
}
/// exposesReturnsTwice - Returns true if the function calls setjmp or
}
/// Return the minimum function alignment.
- unsigned getMinFunctionLogAlignment() const {
- return Log2(MinFunctionAlignment);
- }
+ llvm::Align getMinFunctionAlignment() const { return MinFunctionAlignment; }
/// Return the preferred function alignment.
- unsigned getPrefFunctionLogAlignment() const {
- return Log2(PrefFunctionAlignment);
- }
+ llvm::Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
/// Return the preferred loop alignment.
virtual llvm::Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
EmitLinkage(&F, CurrentFnSym);
if (MAI->hasFunctionAlignment())
- EmitAlignment(MF->getLogAlignment(), &F);
+ EmitAlignment(Log2(MF->getAlignment()), &F);
if (MAI->hasDotTypeDotSizeDirective())
OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_ELF_TypeFunction);
// We want our funclet's entry point to be aligned such that no nops will be
// present after the label.
Asm->EmitAlignment(
- std::max(Asm->MF->getLogAlignment(), MBB.getLogAlignment()), &F);
+ Log2(std::max(Asm->MF->getAlignment(), MBB.getAlignment())), &F);
// Now that we've emitted the alignment directive, point at our funclet.
Asm->OutStreamer->EmitLabel(Sym);
/// Compute the offset immediately following this block. \p MBB is the next
/// block.
unsigned postOffset(const MachineBasicBlock &MBB) const {
- unsigned PO = Offset + Size;
- unsigned LogAlign = MBB.getLogAlignment();
- if (LogAlign == 0)
+ const unsigned PO = Offset + Size;
+ const llvm::Align Align = MBB.getAlignment();
+ if (Align == 1)
return PO;
- unsigned AlignAmt = 1 << LogAlign;
- unsigned ParentLogAlign = MBB.getParent()->getLogAlignment();
- if (LogAlign <= ParentLogAlign)
- return PO + OffsetToAlignment(PO, AlignAmt);
+ const llvm::Align ParentAlign = MBB.getParent()->getAlignment();
+ if (Align <= ParentAlign)
+ return PO + OffsetToAlignment(PO, Align.value());
// The alignment of this MBB is larger than the function's alignment, so we
// can't tell whether or not it will insert nops. Assume that it will.
- return PO + AlignAmt + OffsetToAlignment(PO, AlignAmt);
+ return PO + Align.value() + OffsetToAlignment(PO, Align.value());
}
};
}
if (YamlMF.Alignment)
- MF.setLogAlignment(Log2_32(YamlMF.Alignment));
+ MF.setAlignment(llvm::Align(YamlMF.Alignment));
MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
MF.setHasWinCFI(YamlMF.HasWinCFI);
yaml::MachineFunction YamlMF;
YamlMF.Name = MF.getName();
- YamlMF.Alignment = 1UL << MF.getLogAlignment();
+ YamlMF.Alignment = MF.getAlignment().value();
YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
YamlMF.HasWinCFI = MF.hasWinCFI();
FrameInfo->ensureMaxAlignment(F.getFnStackAlignment());
ConstantPool = new (Allocator) MachineConstantPool(getDataLayout());
- LogAlignment = STI->getTargetLowering()->getMinFunctionLogAlignment();
+ Alignment = STI->getTargetLowering()->getMinFunctionAlignment();
// FIXME: Shouldn't use pref alignment if explicit alignment is set on F.
// FIXME: Use Function::hasOptSize().
if (!F.hasFnAttribute(Attribute::OptimizeForSize))
- LogAlignment = std::max(
- LogAlignment, STI->getTargetLowering()->getPrefFunctionLogAlignment());
+ Alignment = std::max(Alignment,
+ STI->getTargetLowering()->getPrefFunctionAlignment());
if (AlignAllFunctions)
- LogAlignment = AlignAllFunctions;
+ Alignment = llvm::Align(1ULL << AlignAllFunctions);
JumpTableInfo = nullptr;
MIB.add(MO);
FirstActualI->eraseFromParent();
- MF.ensureLogAlignment(4);
+ MF.ensureAlignment(llvm::Align(16));
return true;
}
// The starting address of all shader programs must be 256 bytes aligned.
// Regular functions just need the basic required instruction alignment.
- MF.setLogAlignment(MFI->isEntryFunction() ? 8 : 2);
+ MF.setAlignment(MFI->isEntryFunction() ? llvm::Align(256) : llvm::Align(4));
SetupMachineFunction(MF);
// Functions needs to be cacheline (256B) aligned.
- MF.ensureLogAlignment(8);
+ MF.ensureAlignment(llvm::Align(256));
SetupMachineFunction(MF);
explicit ARCFunctionInfo(MachineFunction &MF)
: ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
ReturnStackOffset(-1U), MaxCallStackReq(0) {
- // Functions are 4-byte (2**2) aligned.
- MF.setLogAlignment(2);
+ // Functions are 4-byte aligned.
+ MF.setAlignment(llvm::Align(4));
}
~ARCFunctionInfo() {}
// tBR_JTr contains a .align 2 directive.
if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
BBI.PostAlign = 2;
- MBB->getParent()->ensureLogAlignment(2);
+ MBB->getParent()->ensureAlignment(llvm::Align(4));
}
}
// Functions with jump tables need an alignment of 4 because they use the ADR
// instruction, which aligns the PC to 4 bytes before adding an offset.
if (!T2JumpTables.empty())
- MF->ensureLogAlignment(2);
+ MF->ensureAlignment(llvm::Align(4));
/// Remove dead constant pool entries.
MadeChange |= removeUnusedCPEntries();
// The function needs to be as aligned as the basic blocks. The linker may
// move functions around based on their alignment.
- MF->ensureLogAlignment(BB->getLogAlignment());
+ MF->ensureAlignment(BB->getAlignment());
// Order the entries in BB by descending alignment. That ensures correct
// alignment of all entries as long as BB is sufficiently aligned. Keep
BBInfoVector &BBInfo = BBUtils->getBBInfo();
// The known bits of the entry block offset are determined by the function
// alignment.
- BBInfo.front().KnownBits = MF->getLogAlignment();
+ BBInfo.front().KnownBits = Log2(MF->getAlignment());
// Compute block offsets and known bits.
BBUtils->adjustBBOffsetsAfter(&MF->front());
// the offset of the instruction. Also account for unknown alignment padding
// in blocks between CPE and the user.
if (CPEOffset < UserOffset)
- UserOffset += Growth + UnknownPadding(MF->getLogAlignment(), CPELogAlign);
+ UserOffset +=
+ Growth + UnknownPadding(Log2(MF->getAlignment()), CPELogAlign);
} else
// CPE fits in existing padding.
Growth = 0;
// Try to split the block so it's fully aligned. Compute the latest split
// point where we can add a 4-byte branch instruction, and then align to
// LogAlign which is the largest possible alignment in the function.
- unsigned LogAlign = MF->getLogAlignment();
+ unsigned LogAlign = Log2(MF->getAlignment());
assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
unsigned KnownBits = UserBBI.internalKnownBits();
unsigned UPad = UnknownPadding(LogAlign, KnownBits);
// NaCl sandboxing requires that indirect call instructions are masked.
// This means that function entry points should be bundle-aligned.
if (Subtarget->isTargetNaCl())
- EmitAlignment(std::max(MF->getLogAlignment(), MIPS_NACL_BUNDLE_LOG_ALIGN));
+ EmitAlignment(
+ std::max(Log2(MF->getAlignment()), MIPS_NACL_BUNDLE_LOG_ALIGN));
if (Subtarget->inMicroMipsMode()) {
TS.emitDirectiveSetMicroMips();
// The function needs to be as aligned as the basic blocks. The linker may
// move functions around based on their alignment.
- MF->ensureLogAlignment(BB->getLogAlignment());
+ MF->ensureAlignment(BB->getAlignment());
// Order the entries in BB by descending alignment. That ensures correct
// alignment of all entries as long as BB is sufficiently aligned. Keep
// Try to split the block so it's fully aligned. Compute the latest split
// point where we can add a 4-byte branch instruction, and then align to
// LogAlign which is the largest possible alignment in the function.
- unsigned LogAlign = MF->getLogAlignment();
+ unsigned LogAlign = Log2(MF->getAlignment());
assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
unsigned BaseInsertOffset = UserOffset + U.getMaxDisp();
LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",
/// original Offset.
unsigned PPCBSel::GetAlignmentAdjustment(MachineBasicBlock &MBB,
unsigned Offset) {
- unsigned LogAlign = MBB.getLogAlignment();
- if (!LogAlign)
+ const llvm::Align Align = MBB.getAlignment();
+ if (Align == 1)
return 0;
- unsigned AlignAmt = 1 << LogAlign;
- unsigned ParentLogAlign = MBB.getParent()->getLogAlignment();
+ const llvm::Align ParentAlign = MBB.getParent()->getAlignment();
- if (LogAlign <= ParentLogAlign)
- return OffsetToAlignment(Offset, AlignAmt);
+ if (Align <= ParentAlign)
+ return OffsetToAlignment(Offset, Align.value());
// The alignment of this MBB is larger than the function's alignment, so we
// can't tell whether or not it will insert nops. Assume that it will.
if (FirstImpreciseBlock < 0)
FirstImpreciseBlock = MBB.getNumber();
- return AlignAmt + OffsetToAlignment(Offset, AlignAmt);
+ return Align.value() + OffsetToAlignment(Offset, Align.value());
}
/// We need to be careful about the offset of the first block in the function
Terminators.clear();
Terminators.reserve(NumBlocks);
- BlockPosition Position(MF->getLogAlignment());
+ BlockPosition Position(Log2(MF->getAlignment()));
for (unsigned I = 0; I < NumBlocks; ++I) {
MachineBasicBlock *MBB = MF->getBlockNumbered(I);
MBBInfo &Block = MBBs[I];
// must be long.
void SystemZLongBranch::setWorstCaseAddresses() {
SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
- BlockPosition Position(MF->getLogAlignment());
+ BlockPosition Position(Log2(MF->getAlignment()));
for (auto &Block : MBBs) {
skipNonTerminators(Position, Block);
for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
// Run a shortening pass and relax any branches that need to be relaxed.
void SystemZLongBranch::relaxBranches() {
SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
- BlockPosition Position(MF->getLogAlignment());
+ BlockPosition Position(Log2(MF->getAlignment()));
for (auto &Block : MBBs) {
skipNonTerminators(Position, Block);
for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
# Make sure we map FPEXT on FPR register bank.
# CHECK-LABEL: name: fp16Ext32
name: fp16Ext32
-alignment: 2
+alignment: 4
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# Make sure we map FPEXT on FPR register bank.
# CHECK-LABEL: name: fp16Ext64
name: fp16Ext64
-alignment: 2
+alignment: 4
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# Make sure we map FPEXT on FPR register bank.
# CHECK-LABEL: name: fp32Ext64
name: fp32Ext64
-alignment: 2
+alignment: 4
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: %0:fpr(s16) = COPY $h0
# CHECK-NEXT: $h0 = COPY %0(s16)
name: passFp16
-alignment: 2
+alignment: 4
legalized: true
registers:
- { id: 0, class: _ }
# CHECK-NEXT: %2:fpr(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
# CHECK-NEXT: $h0 = COPY %2(s16)
name: passFp16ViaAllocas
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
registers:
...
---
name: test_anyext_crash
-alignment: 2
+alignment: 4
legalized: false
registers:
- { id: 0, class: _, preferred-register: '' }
...
---
name: fcmp_more_than_one_user_no_fold
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: using_icmp
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: foeq
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fueq
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fone
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fune
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: doeq
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: dueq
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: done
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: dune
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: copy_from_physreg
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: eq
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: using_fcmp
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: x
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: fp16_to_gpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: gpr_to_fp16
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: gpr_to_fp16_physreg
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_memcpy1
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_memcpy2_const
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_memcpy3_const_arrays_unaligned
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_memmove1
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: test_memmove2_const
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: test_memmove3_const_toolarge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: test_memmove4_const_unaligned
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: test_ms1
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: test_ms2_const
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: test_ms3_const_both
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: test_ms4_const_both_unaligned
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: test_small_memcpy
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_large_memcpy
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: add_v8i16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: add_v16i8
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_blockaddress
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8f16.ceil
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f16.ceil
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_s128
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_s128
...
---
name: test_v4f16.cos
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8f16.cos
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f32.cos
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f32.cos
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f64.cos
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_cos_half
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: sdiv_v4s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_simple_alloca
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
...
---
name: test_aligned_alloca
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
...
---
name: test_natural_alloca
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
...
---
name: test_v4f16.exp
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8f16.exp
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f32.exp
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f32.exp
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f64.exp
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_exp_half
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_zext_v8s16_from_v8s8
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_sext_v8s16_from_v8s8
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_anyext_v8s16_from_v8s8
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_zext_v4s32_from_v4s16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_sext_v4s32_from_v4s16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_anyext_v4s32_from_v4s16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_zext_v2s64_from_v2s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_sext_v2s64_from_v2s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_anyext_v2s64_from_v2s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f16.exp2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v8f16.exp2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v2f32.exp2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v4f32.exp2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v2f64.exp2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_exp2_half
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v4f16.fma
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v8f16.fma
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v2f32.fma
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v4f32.fma
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v2f64.fma
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - | FileCheck %s --check-prefix=FP16
name: test_f16.rint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_f32.rint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_f64.rint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v4f32.rint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v2f64.rint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v4f16.rint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v8f16.rint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v2f32.rint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_f16.round
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_f32.round
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_f64.round
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v8f16.round
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v4f16.round
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f32.round
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f32.round
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f64.round
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_f16.intrinsic_trunc
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v4f16.intrinsic_trunc
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v8f16.intrinsic_trunc
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v2f32.intrinsic_trunc
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v4f32.intrinsic_trunc
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v2f64.intrinsic_trunc
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
---
name: broken
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
---
name: broken
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: store_v2p0
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: load_v2p0
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: load_v2p1
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: store_4xi16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: store_4xi32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: store_8xi16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: store_16xi8
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: load_4xi16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: load_4xi32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: load_8xi16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: load_16xi8
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: load_8xi8
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v4f16.log
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8f16.log
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f32.log
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f32.log
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f64.log
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_log_half
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f16.log10
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8f16.log10
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f32.log10
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f32.log10
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f64.log10
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_log10_half
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f16.log2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8f16.log2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f32.log2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f32.log2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f64.log2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_log2_half
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f16.nearbyint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v8f16.nearbyint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v2f32.nearbyint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_v2f64.nearbyint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_f32.nearbyint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_f64.nearbyint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test_f16.nearbyint
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: load_store_test
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
...
---
name: legalize_phi
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: legalize_phi_ptr
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: legalize_phi_empty
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: legalize_phi_loop
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: legalize_phi_cycle
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: legalize_phi_same_bb
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: legalize_phi_diff_bb
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_v4f16.pow
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v8f16.pow
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v2f32.pow
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v4f32.pow
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: test_v2f64.pow
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: udiv_test
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
...
---
name: sdiv_test
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
...
---
name: v2s64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
...
---
name: v2s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0:
# RUN: llc -mtriple=aarch64 -O0 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
---
name: shuffle_v4i32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1:
...
---
name: shuffle_v2i64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1:
...
---
name: shuffle_1elt_mask
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1:
...
---
name: test_v4f16.sin
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8f16.sin
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f32.sin
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f32.sin
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2f64.sin
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_sin_half
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8f16.sqrt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4f16.sqrt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
---
name: test_v2i64_eq
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i32_eq
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i32_eq
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i16_eq
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i16_eq
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v16i8_eq
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i8_eq
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i64_ugt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i32_ugt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i32_ugt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i16_ugt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i16_ugt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v16i8_ugt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i8_ugt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i64_uge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i32_uge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i32_uge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i16_uge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i16_uge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v16i8_uge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i8_uge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i64_ult
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i32_ult
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i32_ult
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i16_ult
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i16_ult
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v16i8_ult
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i8_ult
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i64_ule
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i32_ule
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i32_ule
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i16_ule
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i16_ule
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v16i8_ule
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i8_ule
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i64_sgt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i32_sgt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i32_sgt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i16_sgt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i16_sgt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v16i8_sgt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i8_sgt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i64_sge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i32_sge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i32_sge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i16_sge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i16_sge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v16i8_sge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i8_sge
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i64_slt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i32_slt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i32_slt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i16_slt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i16_slt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v16i8_slt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i8_slt
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i64_sle
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i32_sle
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2i32_sle
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i16_sle
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v4i16_sle
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v16i8_sle
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v8i8_sle
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_v2p0_eq
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
# This test checks we don't crash when doing zext(trunc) legalizer combines.
---
name: zext_trunc_dead_inst_crash
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: zext_trunc_dead_inst_crash
---
name: ldrxrox_breg_oreg
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: ldrdrox_breg_oreg
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: more_than_one_use
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrxrox_shl
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrdrox_shl
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrxrox_mul_rhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrdrox_mul_rhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrxrox_mul_lhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrdrox_mul_lhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: mul_not_pow_2
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: mul_wrong_pow_2
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: more_than_one_use_shl_1
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: more_than_one_use_shl_2
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: more_than_one_use_shl_lsl_fast
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: more_than_one_use_shl_lsl_slow
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: more_than_one_use_shl_minsize
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrwrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrsrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrhrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldbbrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ldrqrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
# CHECK-LABEL: name: foo
name: foo
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_inttoptr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: int_extensions
-alignment: 2
+alignment: 4
legalized: false
regBankSelected: false
selected: false
...
---
name: ld_zext_i24
-alignment: 2
+alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: cmn_s32_rhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: cmn_s32_lhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: no_cmn_s32_rhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: no_cmn_s32_lhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: cmn_s64_rhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: cmn_s64_lhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: no_cmn_s64_rhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: no_cmn_s64_lhs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: tst_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: tst_s64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: no_tst_unsigned_compare
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: no_tst_nonzero
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: imm_tst
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: no_imm_tst_not_logical_imm
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_physreg_copy
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -O1 -verify-machineinstrs %s -o - | FileCheck %s
---
name: splat_4xi32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: splat_2xi64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: splat_4xf32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: splat_2xf64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: splat_2xf64_copies
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: not_all_zeros
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
name: v2s32_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
registers:
...
---
name: v4s32_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
registers:
...
---
name: v2s64_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
registers:
...
---
name: v4s16_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
registers:
# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
---
name: extract_s64_s128
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
---
name: fma_f32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: fma_f64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
# 3) The fourth operand should be a GPR, since it's a constant.
name: v4s32_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: v4s32_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: v2s64_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: v2s64_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: v2s32_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: v2s32_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: test_f16.round
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_f32.round
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_f64.round
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_v8f16.round
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_v4f16.round
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_v2f32.round
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_v4f32.round
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_v2f64.round
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_f32.intrinsic_trunc
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_f64.intrinsic_trunc
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: test_v4f16.nearbyint
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: test_v8f16.nearbyint
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: test_v2f32.nearbyint
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: test_v2f64.nearbyint
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: test_f32.nearbyint
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: test_f64.nearbyint
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: test_f16.nearbyint
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: select_f32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: select_f64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: two_fpr_inputs_gpr_output
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: one_fpr_input_fpr_output
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: one_fpr_input_gpr_output
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
...
---
name: two_gpr_input_fpr_output
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
---
name: trunc_s64_s128
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
---
name: build_vec_f16
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
---
name: unmerge
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
...
---
name: unmerge_s128
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
frameInfo:
---
name: add_sext_s32_to_s64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_and_s32_to_s64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_sext_s16_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_zext_s16_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_anyext_s16_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_and_s16_to_s32_uxtb
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_and_s16_to_s32_uxth
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_sext_s8_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_zext_s8_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_anyext_s8_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_sext_with_shl
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_and_with_shl
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: dont_fold_invalid_mask
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: dont_fold_invalid_shl
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_sext_s32_to_s64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_sext_s16_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_zext_s16_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_anyext_s16_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_and_s16_to_s32_uxtb
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_and_s16_to_s32_uxth
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
RET_ReallyLR implicit $w3
---
name: sub_sext_s8_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_zext_s8_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_anyext_s8_to_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_sext_with_shl
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_and_with_shl
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: load_acq_i8
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_v8i16
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: add_v16i8
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_blockaddress
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: bswap_v4s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: bswap_v2s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: bswap_v2s64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f32
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_f64
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_i32
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_i64
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_p0
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_rhs_inttoptr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rhs_unknown
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: legal_v4s32_v2s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: legal_v8s16_v4s16
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s
name: test_v8s8
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4s16
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_s64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16s8
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8s16
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2s64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v2s32_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v2s32_fpr_idx0
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v2s64_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v4s16_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v8s16_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v8s16_fpr_zext
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v8s16_fpr_sext
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v8s16_fpr_trunc
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zero
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: notzero
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f16.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4f16.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8f16.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f16.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f32.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f64.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4f32.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2f64.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4f16.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8f16.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2f32.rint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
name: v4s32_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v4s32_gpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v2s64_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v2s64_gpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v2s32_fpr
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: v2s32_gpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: anyext_v8s16_from_v8s8
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: anyext_v4s32_from_v4s16
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: anyext_v2s64_from_v2s32
-alignment: 2
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tracksRegLiveness: true
legalized: true
regBankSelected: true
---
name: zext_v8s16_from_v8s8
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: zext_v4s32_from_v4s16
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: zext_v2s64_from_v2s32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: sext_v8s16_from_v8s8
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: sext_v4s32_from_v4s16
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: sext_v2s64_from_v2s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f64.intrinsic_round
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f32.intrinsic_round
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f16.intrinsic_round
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4f16.intrinsic_round
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8f16.intrinsic_round
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2f32.intrinsic_round
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4f32.intrinsic_round
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2f64.intrinsic_round
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f64.intrinsic_trunc
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f32.intrinsic_trunc
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f16.intrinsic_trunc
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4f16.intrinsic_trunc
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8f16.intrinsic_trunc
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2f32.intrinsic_trunc
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4f32.intrinsic_trunc
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2f64.intrinsic_trunc
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: jt_test
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: test_load_acquire_i8
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_load_acquire_i16
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_load_acquire_i32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_load_acquire_i64
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_load_i8
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_load_i16
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_load_i32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_load_i64
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: store_v2p0
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: load_v2p0
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: load_4xi16
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: load_4xi32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: load_8xi16
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: load_16xi8
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4f16.nearbyint
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8f16.nearbyint
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2f32.nearbyint
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2f64.nearbyint
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f32.nearbyint
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f64.nearbyint
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_f16.nearbyint
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_phi
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
---
name: test_phi_ptr
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: main
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exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: select_f32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: select_f64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: shuffle_v2f32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: shuffle_v4i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: shuffle_tbl_v4i32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: shuffle_v2i64
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: shuffle_undef_mask_elt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_store_release_i64
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_store_release_i32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_store_release_i8
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_store_release_i16
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: store_4xi16
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: store_4xi32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: store_8xi16
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: store_16xi8
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_store_i8
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_store_i16
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_store_i32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_store_i64
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: foo
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: uaddo_s32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: uaddo_s64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2s64_unmerge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4s32_unmerge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4s16_unmerge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8s16_unmerge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_vecsplit_2v2s32_v4s32
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_vecsplit_2v2s16_v4s16
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_s128
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_eq
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_eq
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_eq
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_eq
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_eq
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_eq
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_eq
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_eq
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_ne
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_ne
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_ne
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_ne
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_ne
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_ne
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_ne
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_ne
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_ugt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_ugt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_ugt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_ugt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_ugt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_ugt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_ugt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_ugt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_uge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_uge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_uge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_uge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_uge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_uge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_uge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_uge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_ult
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_ult
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_ult
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_ult
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_ult
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_ult
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_ult
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_ult
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_ule
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_ule
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_ule
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_ule
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_ule
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_ule
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_ule
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_ule
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_sgt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_sgt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_sgt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_sgt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_sgt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_sgt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_sgt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_sgt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_sge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_sge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_sge
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_sge
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_sge
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_sge
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_sge
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_sge
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_slt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_slt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_slt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_slt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_slt
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_slt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_slt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_slt
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i64_sle
-alignment: 2
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legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i32_sle
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i32_sle
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v2i16_sle
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i16_sle
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v4i16_sle
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v16i8_sle
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_v8i8_sle
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: shl_v2i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: shl_v4i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ashr_v2i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ashr_v4i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
# RUN: -o - | FileCheck %s
---
name: test_rule14_id188_at_idx1067
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule21_id2237_at_idx1449
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule22_id2238_at_idx1505
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule27_id2243_at_idx1781
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule28_id2244_at_idx1837
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule29_id2245_at_idx1893
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule30_id2246_at_idx1949
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule34_id2250_at_idx2173
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
# The rules that generated this test has changed. The generator should be rerun
---
name: test_rule92_id2150_at_idx7770
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
# The rules that generated this test has changed. The generator should be rerun
---
name: test_rule96_id2146_at_idx8070
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule129_id2130_at_idx10828
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule130_id2131_at_idx10884
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule135_id2136_at_idx11160
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule136_id2137_at_idx11216
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule137_id2138_at_idx11272
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule138_id2139_at_idx11328
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule339_id2369_at_idx26608
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule340_id2370_at_idx26714
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule341_id2371_at_idx26820
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule342_id2372_at_idx26926
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule343_id1266_at_idx27032
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule344_id1268_at_idx27128
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule345_id1270_at_idx27224
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule346_id1326_at_idx27320
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule347_id1328_at_idx27416
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule348_id1330_at_idx27512
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule349_id1308_at_idx27608
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule350_id1310_at_idx27704
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule351_id1312_at_idx27800
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule352_id1356_at_idx27896
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule353_id1358_at_idx27992
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule354_id1360_at_idx28088
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule928_id2367_at_idx60019
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule929_id2368_at_idx60105
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule930_id2446_at_idx60191
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule931_id2447_at_idx60277
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule932_id2448_at_idx60363
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule934_id429_at_idx60537
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule935_id430_at_idx60625
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule938_id899_at_idx60889
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule939_id900_at_idx60977
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule940_id901_at_idx61065
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule942_id435_at_idx61241
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule943_id436_at_idx61329
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule944_id3803_at_idx61417
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule945_id3804_at_idx61505
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule946_id3805_at_idx61593
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule947_id3806_at_idx61681
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule950_id3869_at_idx61945
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule951_id3871_at_idx62021
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule952_id3873_at_idx62097
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule953_id3887_at_idx62173
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule954_id3889_at_idx62249
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule955_id3891_at_idx62325
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule956_id927_at_idx62401
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule957_id928_at_idx62489
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule958_id929_at_idx62577
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule959_id930_at_idx62665
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule962_id1272_at_idx62929
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule963_id1274_at_idx63005
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule964_id1276_at_idx63081
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule965_id1332_at_idx63157
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule966_id1334_at_idx63233
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule967_id1336_at_idx63309
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule977_id933_at_idx64051
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule978_id934_at_idx64139
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule979_id935_at_idx64227
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule980_id936_at_idx64315
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule983_id1314_at_idx64579
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule984_id1316_at_idx64655
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule985_id1318_at_idx64731
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule986_id1362_at_idx64807
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule987_id1364_at_idx64883
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule988_id1366_at_idx64959
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule990_id432_at_idx65123
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule991_id433_at_idx65211
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule993_id420_at_idx65375
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule994_id421_at_idx65451
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1230_id2969_at_idx81784
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1231_id2970_at_idx81816
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1239_id894_at_idx82201
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1240_id895_at_idx82269
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1241_id896_at_idx82337
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1244_id751_at_idx82487
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1245_id752_at_idx82530
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1246_id753_at_idx82573
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1247_id754_at_idx82616
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1254_id1162_at_idx82913
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1255_id1163_at_idx82956
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1256_id1751_at_idx82999
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1259_id1754_at_idx83128
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1268_id829_at_idx83513
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1269_id830_at_idx83556
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1270_id831_at_idx83599
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1276_id849_at_idx83857
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1277_id850_at_idx83900
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1278_id851_at_idx83943
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1284_id909_at_idx84201
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1285_id910_at_idx84244
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1286_id911_at_idx84287
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1292_id924_at_idx84545
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1293_id925_at_idx84588
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1294_id926_at_idx84631
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1296_id939_at_idx84715
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1297_id940_at_idx84758
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1298_id941_at_idx84801
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1299_id942_at_idx84844
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1304_id1174_at_idx85055
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1305_id1175_at_idx85098
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1306_id1827_at_idx85141
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1309_id1830_at_idx85270
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1315_id1051_at_idx85522
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1316_id1052_at_idx85565
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1317_id1053_at_idx85608
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1318_id1054_at_idx85651
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1329_id1170_at_idx86118
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1330_id1171_at_idx86161
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1331_id1791_at_idx86204
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1334_id1794_at_idx86333
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1337_id2925_at_idx86462
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1338_id2928_at_idx86507
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1339_id2931_at_idx86552
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1582_id372_at_idx97075
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1583_id373_at_idx97110
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1586_id597_at_idx97215
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1587_id598_at_idx97250
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1588_id599_at_idx97285
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1592_id2383_at_idx97425
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1593_id2385_at_idx97458
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1602_id587_at_idx97771
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1603_id588_at_idx97806
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1604_id589_at_idx97841
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1613_id592_at_idx98156
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1614_id593_at_idx98191
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1615_id594_at_idx98226
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1619_id2389_at_idx98366
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1620_id2390_at_idx98399
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1621_id2923_at_idx98432
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1622_id2926_at_idx98477
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1623_id2929_at_idx98522
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1632_id687_at_idx98847
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1633_id688_at_idx98882
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1634_id689_at_idx98917
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1635_id748_at_idx98952
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1636_id749_at_idx98987
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1637_id750_at_idx99022
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1647_id731_at_idx99386
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1648_id732_at_idx99421
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1649_id733_at_idx99456
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1650_id2924_at_idx99491
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1651_id2927_at_idx99536
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_rule1652_id2930_at_idx99581
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: strxrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: strdrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: strwrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: strsrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: strhrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: strqrox
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: shl
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: main
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_q10_q11_x19_x20
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0.entry:
...
---
name: test
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
...
---
name: compiler_pop_stack
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$w0' }
...
---
name: f
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
...
---
name: f
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_jumptable
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0 (%ir-block.0):
...
---
name: foo2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0 (%ir-block.0):
...
---
name: foo3
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.0 (%ir-block.0):
...
---
name: test_mov_0
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: false
frameInfo:
# false.
name: baz
# CHECK-LABEL: name: baz
-alignment: 2
+alignment: 4
tracksRegLiveness: true
frameInfo:
adjustsStack: true
...
---
name: foobar
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
...
---
name: test
-alignment: 2
+alignment: 4
tracksRegLiveness: true
hasWinCFI: true
liveins:
...
---
name: test
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: '?func@@YAHH@Z'
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: '?func@@YAHHHHH@Z'
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: '?func@@YAHH@Z'
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: '?func@@YAHH@Z'
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test
-alignment: 2
+alignment: 4
tracksRegLiveness: true
hasWinCFI: true
liveins:
...
---
name: test
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: '?func@@YAHH@Z'
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: '?func@@YAHHHHH@Z'
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: '?func@@YAHHHHH@Z'
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: '?func@@YAHHH@Z'
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_blockaddress
-alignment: 4
+alignment: 16
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
...
---
name: test_blockaddress
-alignment: 4
+alignment: 16
legalized: true
body: |
bb.1 (%ir-block.0):
---
name: main
-alignment: 0
+alignment: 1
tracksRegLiveness: true
registers:
- { id: 0, class: sreg_64 }
# GCN: %10:vgpr_32 = V_MOV_B32_e32 1543, implicit $exec
# GCN: BUFFER_STORE_DWORD_OFFSET killed %10,
name: s_fold_and_imm_regimm_32
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: FLAT_STORE_DWORD %19, %13,
name: v_fold_and_imm_regimm_32
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: BUFFER_STORE_DWORD_OFFSET killed %13,
name: s_fold_shl_imm_regimm_32
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: FLAT_STORE_DWORD %20, %28,
name: v_fold_shl_imm_regimm_32
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: %11:vgpr_32 = V_MOV_B32_e32 243, implicit $exec
# GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8,
name: s_fold_ashr_imm_regimm_32
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: FLAT_STORE_DWORD %20, %28,
name: v_fold_ashr_imm_regimm_32
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: %11:vgpr_32 = V_MOV_B32_e32 1048332, implicit $exec
# GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8,
name: s_fold_lshr_imm_regimm_32
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: FLAT_STORE_DWORD %20, %28,
name: v_fold_lshr_imm_regimm_32
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN-NEXT: S_ENDPGM 0, implicit %2
name: constant_fold_lshl_or_reg0_immreg_reg
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN-NEXT: S_ENDPGM 0, implicit %2
name: constant_fold_lshl_or_reg0_immreg_imm
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN-NEXT: S_ENDPGM 0, implicit %3
name: constant_fold_lshl_or_reg0_immreg_immreg
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _amdgpu_ps_main
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: main
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: flat_load_clustering
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: %13:vgpr_32 = V_ADD_F16_e32 1065353216, killed %11, implicit $exec
name: add_f32_1.0_one_f16_use
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
name: add_f32_1.0_multi_f16_use
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: %16:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $exec
name: add_f32_1.0_one_f32_use_one_f16_use
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: %17:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $exec
name: add_f32_1.0_one_f32_use_multi_f16_use
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
name: add_i32_1_multi_f16_use
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: %17:vgpr_32 = V_ADD_F32_e32 -2, killed %13, implicit $exec
name: add_i32_m2_one_f32_use_multi_f16_use
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: %15:vgpr_32 = V_ADD_F32_e32 %12, %13, implicit $exec
name: add_f16_1.0_multi_f32_use
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $exec
name: add_f16_1.0_other_high_bits_multi_f16_use
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $exec
name: add_f16_1.0_other_high_bits_use_f16_f32
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: hazard_implicit_def
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: V_INTERP_P1_F32
---
name: hazard_inlineasm
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: $vgpr2 = V_MOV_B32
# CHECK: $vgpr3 = V_MOV_B32
name: exp_done_waitcnt
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: mov_fed_hazard_crash_on_dbg_value
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
name: invert_br_undef_vcc
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: main
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK-NEXT: BUFFER_WBINVL1_VOL
name: atomic_max_i32_noret
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 1, 1, 0, 0
name: multiple_mem_operands
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0
name: multiple_mem_operands
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: scc_def_and_use_no_dependency
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: S_ADDC_U32
---
name: scc_def_and_use_dependency
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: mem_dependency
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: const_to_sgpr
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: const_to_sgpr_multiple_use
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: const_to_sgpr_subreg
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: undef %18.sub0:vreg_128 = V_MAC_F32_e32 undef %3:vgpr_32, undef %9:vgpr_32, undef %18.sub0, implicit $exec
name: mac_invalid_operands
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0,
# GCN: BUFFER_STORE_DWORD_OFFEN %7.sub0, %0,
name: vreg_does_not_dominate
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: DBG_VALUE %99, $noreg, !5, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !8
name: sched_dbg_value_crash
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: mo_pset
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: sdwa_imm_operand
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: sdwa_sgpr_operand
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %19, %17, 0, implicit $exec
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
name: shrink_add_vop3
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
name: shrink_sub_vop3
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
name: shrink_subrev_vop3
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
name: check_addc_src2_vop3
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
name: shrink_addc_vop3
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
name: shrink_addc_undef_vcc
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: _amdgpu_cs_main
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK-NEXT: $sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
# CHECK: $exec = COPY killed $sgpr2_sgpr3
name: undefined_physreg_sgpr_spill
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4, addrspace 5)
# CHECK: $exec = COPY killed $sgpr2_sgpr3
name: undefined_physreg_sgpr_spill_reorder
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
name: vccz_corrupt_workaround
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK-NEXT: $vgpr0 = V_MOV_B32_e32
name: vccz_corrupt_undef_vcc
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
#CHECK: S_CMP_LT_I32
#CHECK: S_CSELECT_B32
name: test_wwm_scc
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: f
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
---
name: f
# CHECK-LABEL: name: f
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: g
# CHECK-LABEL: name: g
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: func
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_split_cfg
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: h
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: func
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
...
---
name: test2
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
...
---
name: test3
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
...
---
name: ARM
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0' }
...
---
name: THUMB
-alignment: 1
+alignment: 2
tracksRegLiveness: true
frameInfo:
stackSize: 8
...
---
name: CP
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: CP
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: fn1
-alignment: 1
+alignment: 2
tracksRegLiveness: true
body: |
bb.0:
...
---
name: foo
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: ldrd_strd_aa
-alignment: 1
+alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '%0' }
---
# CHECK-LABEL: name: a
name: a
-alignment: 1
+alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '%0' }
---
# CHECK-LABEL: name: b
name: b
-alignment: 1
+alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '%0' }
...
---
name: f
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
...
---
name: foo
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: bar
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 1
+alignment: 2
liveins:
- { reg: '$r0' }
body: |
...
---
name: g
-alignment: 1
+alignment: 2
tracksRegLiveness: true
body: |
bb.0:
...
---
name: f0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
liveins:
...
---
name: f0
-alignment: 4
+alignment: 16
registers:
- { id: 0, class: intregs, preferred-register: '' }
- { id: 1, class: intregs, preferred-register: '' }
...
---
name: if-cvt
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: foo
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$r0' }
...
---
name: f0
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: main
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: intregs }
...
---
name: test0a
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: test0b
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: test1a
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: test1b
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: test2a
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: test2b
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: test3
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: test4
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: testBB
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
# FALLBACK-LABEL: name: test
# FALLBACK-NOT: failedISel
name: test
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
failedISel: true
---
#CHECK: foo
name: foo
-alignment: 2
+alignment: 4
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
---
#CHECK: bar
name: bar
-alignment: 2
+alignment: 4
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
...
---
name: swp
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64common }
...
---
name: syncscopes
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
# CHECK: name: func
-# CHECK-NEXT: alignment: 8
+# CHECK-NEXT: alignment: 256
# CHECK-NEXT: exposesReturnsTwice: false
# CHECK: ...
name: func
-alignment: 8
+alignment: 256
...
---
# CHECK: name: func2
-# CHECK-NEXT: alignment: 16
+# CHECK-NEXT: alignment: 65536
# CHECK-NEXT: exposesReturnsTwice: true
# CHECK: ...
name: func2
-alignment: 16
+alignment: 65536
exposesReturnsTwice: true
...
# RUN: -simplify-mir %s -o - | FileCheck %s
---
name: poc
-alignment: 4
+alignment: 16
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: poc
---
name: test1BB
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
body: |
---
name: test2BBs
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
body: |
...
---
name: foo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: baz
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: fun
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: len
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
stackSize: 40
...
---
name: foo
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
maxAlignment: 8
...
---
name: test
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
stackSize: 4
...
---
name: test
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
stackSize: 40
...
---
name: add_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: and_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: or_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: xor_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: shl
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ashr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: lshr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: shlv
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ashrv
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: lshrv
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: Unconditional_branch
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: Conditional_branch
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: _0xABCD0000
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: _0x00008000
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: _0xFFFFFFF6
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: _0x0A0B0C0D
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fabs_f32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fabs_f64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: false_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: true_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: uno_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ord_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: oeq_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: une_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ueq_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: one_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: olt_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: uge_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ult_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: oge_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ole_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ugt_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ule_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ogt_s
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: false_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: true_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: uno_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ord_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: oeq_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: une_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ueq_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: one_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: olt_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: uge_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ult_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: oge_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ole_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ugt_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ule_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ogt_d
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: atomic_load_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_in_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_in_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_in_gpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_in_gpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: call_float_in_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: call_double_in_fpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: call_float_in_gpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: call_double_in_gpr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_add
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_sub
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_mul
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_div
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_add
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_sub
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_mul
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_div
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: e_single_precision
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: e_double_precision
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fpext
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fptrunc
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: f32toi32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: f64toi32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sqrt_f32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sqrt_f64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: main
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: f_with_local_linkage
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: call_global
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: call_global_with_local_linkage
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ret_global_int
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ret_global_int_with_local_linkage
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: eq_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ne_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sgt_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sge_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: slt_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sle_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ugt_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: uge_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ult_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ule_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: eq_ptr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: inttoptr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: mod4_0_to_11
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: load_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: load_float
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: load_double
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: _16_bit_positive_offset
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: _16_bit_negative_offset
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: _large_positive_offset
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: _large_negative_offset
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fold_f32_load
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fold_f64_store
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fold_i16_load
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fold_i32_store
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: mul_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: umul_with_overflow
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: phi_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: phi_i64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: phi_float
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: phi_double
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptr_arg_in_regs
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptr_arg_on_stack
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ret_ptr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sdiv_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: srem_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: udiv_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: urem_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: select_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: select_ptr
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: select_float
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: select_double
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: i32tof32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: i32tof64
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: g
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: store_i32
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: store_float
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: store_double
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: sub_i32
-alignment: 2
+alignment: 4
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tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: i32tof64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: i16tof64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: i8tof64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: u64tof32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: u32tof32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: u16tof32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: u8tof32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: u64tof64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: u32tof64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: u16tof64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: u8tof64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: g
-alignment: 2
+alignment: 4
tracksRegLiveness: true
fixedStack:
- { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
...
---
name: store_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: store_i64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: store_float
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: store_double
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: sub_i32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: sub_i8_sext
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: sub_i8_zext
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: sub_i8_aext
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: sub_i16_sext
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: sub_i16_zext
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: sub_i16_aext
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: sub_i64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: sub_i128
-alignment: 2
+alignment: 4
tracksRegLiveness: true
fixedStack:
- { id: 0, offset: 28, size: 4, alignment: 4, stack-id: default, isImmutable: true }
...
---
name: f
-alignment: 2
+alignment: 4
body: |
bb.1 (%ir-block.0):
; MIPS32-LABEL: name: f
...
---
name: trunc
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_load1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load2_s16_to_load2_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load_store_i1
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load_store_i8
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load_store_i16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load_store_i32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_zextLoad1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load2_s16_to_zextLoad2_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_zextLoad1_s16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load4_s32_to_zextLoad4_s64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_sextLoad1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load2_s16_to_sextLoad2_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_sextLoad1_s16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load4_s32_to_sextLoad4_s64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: zext
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: sext
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_load1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load2_s16_to_load2_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
# MIPS32: Try combining $v0 = COPY %2:_(s32)
# MIPS32: Try combining RetRA implicit $v0
name: f
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_zextLoad1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load2_s16_to_zextLoad2_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_zextLoad1_s16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load4_s32_to_zextLoad4_s64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_sextLoad1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load2_s16_to_sextLoad2_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_sextLoad1_s16
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: load4_s32_to_sextLoad4_s64
-alignment: 2
+alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
...
---
name: skipCopiesOutgoing
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: skipCopiesIncoming
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: add_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: and_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: or_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: xor_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: shl
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: ashr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: lshr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: shlv
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: ashrv
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: lshrv
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: Unconditional_branch
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: Conditional_branch
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: fabs_f32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: fabs_f64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: oeq_s
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: oeq_d
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: atomic_load_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: float_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: double_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: float_in_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: double_in_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: call_float_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: call_double_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: call_float_in_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: call_double_in_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: float_add
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: float_sub
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: float_mul
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: float_div
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: double_add
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: double_sub
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: double_mul
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: double_div
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: e_single_precision
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: e_double_precision
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: fpext
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: fptrunc
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: f32toi32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: f64toi32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: sqrt_f32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: sqrt_f64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: main
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: call_global
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: ne_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: eq_ptr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: inttoptr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: ptrtoint
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: mod4_0_to_11
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
jumpTable:
...
---
name: load_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load_i64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load_ambiguous_i64_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load_float
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load_ambiguous_float_in_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load_double
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: long_chain_ambiguous_i64_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: long_chain_i64_in_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: long_chain_ambiguous_double_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: long_chain_double_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: long_chain_ambiguous_i64_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: long_chain_i64_in_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: long_chain_ambiguous_double_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: long_chain_double_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: mul_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: umul_with_overflow
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: phi_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: phi_i64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: phi_ambiguous_i64_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: phi_float
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: phi_ambiguous_float_in_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: phi_double
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: ptr_arg_in_regs
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: ptr_arg_on_stack
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: ret_ptr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: sdiv_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: srem_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: udiv_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: urem_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: select_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: select_ptr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: select_i64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: select_ambiguous_i64_in_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: select_float
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: select_ambiguous_float_in_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: select_double
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: i32tof32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: i32tof64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: g
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
fixedStack:
...
---
name: store_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: store_i64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: store_float
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: store_double
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: sub_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: outgoing_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: outgoing_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: outgoing_gpr_instr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: outgoing_fpr_instr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: incoming_gpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: incoming_fpr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: incoming_i32_instr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: incoming_float_instr
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load_store_i8
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load_store_i16
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load_store_i32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load1_s8_to_zextLoad1_s32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load2_s16_to_zextLoad2_s32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load4_s32_to_zextLoad4_s64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load1_s8_to_sextLoad1_s32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load2_s16_to_sextLoad2_s32
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: load4_s32_to_sextLoad4_s64
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: zext
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
...
---
name: sext
-alignment: 2
+alignment: 4
legalized: true
tracksRegLiveness: true
body: |
# CHECK-NEXT: nop
# CHECK: blezc
name: f
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: l5
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: fooTail
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: fooTail
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the position operand is in the range 0..31
---
name: dext
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the size operand is in the range 1..32
---
name: dext
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the pos + size is in the range 33..64
---
name: dextm
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the position operand is in the range 0..31
---
name: dextm
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the size operand is in the range 33..64
---
name: dextm
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the pos + size is in the range 33..64
---
name: dextu
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the position operand is in the range 32..63
---
name: dextu
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the size operand is in the range 1..32
---
name: dextu
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the size operand is in the range 1..32
---
name: dextu
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the pos + size is in the range 1..32
---
name: dins
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the position operand is in the range 0..31
---
name: dins
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the size operand is in the range 1..32
---
name: dins
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the pos + size is in the range 33..64
---
name: dinsu
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the position operand is in the range 0..31
---
name: dinsm
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the size operand is in the range 2..64
---
name: dinsm
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the pos + size is in the range 33..64
---
name: dinsu
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the position operand is in the range 32..63
---
name: dinsu
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the size operand is in the range 1..32
---
name: dinsu
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the pos + size is in the range 1..32
---
name: f
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the position operand is in the range 0..31
---
name: f
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the size operand is in the range 1..32
---
name: f
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the pos + size is in the range 1..32
---
name: f
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the position operand is in the range 0..31
---
name: f
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# Check that the machine verifier checks the size operand is in the range 1..32
---
name: f
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: a
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: b
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: a
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: b
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: a
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: b
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: a
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: b
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQ_MM
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEZ_MM
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGTZ_MM
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLEZ_MM
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTZ_MM
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNE_MM
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQZ16_MM
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNEZ16_MM
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNEC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEUC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEZC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGTZC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLEZC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTUC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTZC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQZC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNEZC_MMR6
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQ64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNE64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEZ64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGTZ64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLEZ64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTZ64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNEZC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQZC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNEC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTUC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEUC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLEZC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTZC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEZC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGTZC64
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNEC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEUC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEZC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGTZC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLEZC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTUC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTZC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQZC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNEZC
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BEQ
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGEZ
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BGTZ
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLEZ
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BLTZ
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: expand_BNE
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z4bz_8Dv16_a
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z5bz_16Dv8_s
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z5bz_32Dv4_i
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z5bz_64Dv2_x
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z5bz_64_vDv2_x
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z5bnz_8Dv16_a
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z6bnz_16Dv8_s
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z6bnz_32Dv4_i
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z6bnz_64Dv2_x
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z6bnz_64_vDv2_x
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z3foov
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z3barPi
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: caller13
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: SWP_MM
# CHECK: LWP_MM
name: f1
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: SWP_MM
# CHECK: LWP_MM
name: f2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: SWP_MM
# CHECK: LWP_MM
name: f3
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: SWP_MM
# CHECK: LWP_MM
name: f4
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK-NOT: SWP_MM
# CHECK-NOT: LWP_MM
name: f1
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK-NOT: SWP_MM
# CHECK-NOT: LWP_MM
name: f2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK-NOT: SWP_MM
# CHECK-NOT: LWP_MM
name: f3
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK-NOT: SWP_MM
# CHECK-NOT: LWP_MM
name: f4
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z2k1i
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z2k1i
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z2k1i
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z2k1i
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: jrc16 $ra # encoding: [0x47,0xe3]
---
name: a
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: g
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: g2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: c: 60 25 90 03 swr $1, 3($5)
# CHECK-LABEL: g2:
-# CHECK: 12: 60 24 64 00 lwle $1, 0($4)
-# CHECK: 16: 60 24 66 03 lwre $1, 3($4)
-# CHECK: 1a: 60 25 a0 00 swle $1, 0($5)
-# CHECK: 1e: 60 25 a2 03 swre $1, 3($5)
+# CHECK: 14: 60 24 64 00 lwle $1, 0($4)
+# CHECK: 18: 60 24 66 03 lwre $1, 3($4)
+# CHECK: 1c: 60 25 a0 00 swle $1, 0($5)
+# CHECK: 20: 60 25 a2 03 swre $1, 3($5)
...
---
name: test
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: mm_update_next_owner
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
...
---
name: test1
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
tracksRegLiveness: true
frameInfo:
...
---
name: _Z6calleev
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z14TestSinglePredv
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _ZN11xercesc_2_79HashXMLCh6equalsEPKvS2_
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: unsafeAddR0R3
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: unsafeAddR3R0
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: safeAddR0R3
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: safeAddR3R0
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: unsafeLDXR3R0
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: safeLDXZeroR3
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: safeLDXR3R0
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWNM
# CHECK-ALL: name: testRLWNM
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWNM8
# CHECK-ALL: name: testRLWNM8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWNMo
# CHECK-ALL: name: testRLWNMo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWNM8o
# CHECK-ALL: name: testRLWNM8o
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSLW
# CHECK-ALL: name: testSLW
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSLWo
# CHECK-ALL: name: testSLWo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRW
# CHECK-ALL: name: testSRW
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRWo
# CHECK-ALL: name: testSRWo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRAW
# CHECK-ALL: name: testSRAW
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRAWo
# CHECK-ALL: name: testSRAWo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDCL
# CHECK-ALL: name: testRLDCL
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDCLo
# CHECK-ALL: name: testRLDCLo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDCR
# CHECK-ALL: name: testRLDCR
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDCRo
# CHECK-ALL: name: testRLDCRo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSLD
# CHECK-ALL: name: testSLD
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSLDo
# CHECK-ALL: name: testSLDo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRD
# CHECK-ALL: name: testSRD
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRDo
# CHECK-ALL: name: testSRDo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRAD
# CHECK-ALL: name: testSRAD
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRADo
# CHECK-ALL: name: testSRADo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testADD4
# CHECK-ALL: name: testADD4
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testADD8
# CHECK-ALL: name: testADD8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testADDC
# CHECK-ALL: name: testADDC
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testADDC8
# CHECK-ALL: name: testADDC8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testADDCo
# CHECK-ALL: name: testADDCo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testADDI
# CHECK-ALL: name: testADDI
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testADDI8
# CHECK-ALL: name: testADDI8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testANDo
# CHECK-ALL: name: testANDo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testAND8o
# CHECK-ALL: name: testAND8o
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testCMPD
# CHECK-ALL: name: testCMPD
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testCMPDI
# CHECK-ALL: name: testCMPDI
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testCMPDI_F
# CHECK-ALL: name: testCMPDI_F
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testCMPLD
# CHECK-ALL: name: testCMPLD
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testCMPLDI
# CHECK-ALL: name: testCMPLDI
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testCMPW
# CHECK-ALL: name: testCMPW
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testCMPWI
# CHECK-ALL: name: testCMPWI
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testCMPLW
# CHECK-ALL: name: testCMPLW
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testCMPLWI
# CHECK-ALL: name: testCMPLWI
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLBZUX
# CHECK-ALL: name: testLBZUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLBZX
# CHECK-ALL: name: testLBZX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLHZUX
# CHECK-ALL: name: testLHZUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLHZX
# CHECK-ALL: name: testLHZX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLHAUX
# CHECK-ALL: name: testLHAUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLHAX
# CHECK-ALL: name: testLHAX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLWZUX
# CHECK-ALL: name: testLWZUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLWZX
# CHECK-ALL: name: testLWZX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLWAX
# CHECK-ALL: name: testLWAX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLDUX
# CHECK-ALL: name: testLDUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLDX
# CHECK-ALL: name: testLDX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLFDUX
# CHECK-ALL: name: testLFDUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLFDX
# CHECK-ALL: name: testLFDX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLFSUX
# CHECK-ALL: name: testLFSUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLFSX
# CHECK-ALL: name: testLFSX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLXSDX
# CHECK-ALL: name: testLXSDX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLXSSPX
# CHECK-ALL: name: testLXSSPX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLXVX
# CHECK-ALL: name: testLXVX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testOR
# CHECK-ALL: name: testOR
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testOR8
# CHECK-ALL: name: testOR8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testORI
# CHECK-ALL: name: testORI
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testORI8
# CHECK-ALL: name: testORI8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDCL
# CHECK-ALL: name: testRLDCL
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDCLo
# CHECK-ALL: name: testRLDCLo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDCR
# CHECK-ALL: name: testRLDCR
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDCRo
# CHECK-ALL: name: testRLDCRo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDICL
# CHECK-ALL: name: testRLDICL
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDICLo
# CHECK-ALL: name: testRLDICLo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDICLo2
# CHECK-ALL: name: testRLDICLo2
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLDICLo3
# CHECK-ALL: name: testRLDICLo3
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWINM
# CHECK-ALL: name: testRLWINM
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWINMFullReg
# CHECK-ALL: name: testRLWINMFullReg
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWINMFullRegOutOfRange
# CHECK-ALL: name: testRLWINMFullRegOutOfRange
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWINM8
# CHECK-ALL: name: testRLWINM8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWINMo
# CHECK-ALL: name: testRLWINMo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWINMo2
# CHECK-ALL: name: testRLWINMo2
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testRLWINM8o
# CHECK-ALL: name: testRLWINM8o
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSLD
# CHECK-ALL: name: testSLD
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSLDo
# CHECK-ALL: name: testSLDo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRD
# CHECK-ALL: name: testSRD
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRDo
# CHECK-ALL: name: testSRDo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSLW
# CHECK-ALL: name: testSLW
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSLWo
# CHECK-ALL: name: testSLWo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRW
# CHECK-ALL: name: testSRW
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRWo
# CHECK-ALL: name: testSRWo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRAW
# CHECK-ALL: name: testSRAW
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRAWo
# CHECK-ALL: name: testSRAWo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRAD
# CHECK-ALL: name: testSRAD
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSRADo
# CHECK-ALL: name: testSRADo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTBUX
# CHECK-ALL: name: testSTBUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTBX
# CHECK-ALL: name: testSTBX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTHUX
# CHECK-ALL: name: testSTHUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTHX
# CHECK-ALL: name: testSTHX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTWUX
# CHECK-ALL: name: testSTWUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTWX
# CHECK-ALL: name: testSTWX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTDUX
# CHECK-ALL: name: testSTDUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTDX
# CHECK-ALL: name: testSTDX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTFSX
# CHECK-ALL: name: testSTFSX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTFSUX
# CHECK-ALL: name: testSTFSUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTFDX
# CHECK-ALL: name: testSTFDX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTFDUX
# CHECK-ALL: name: testSTFDUX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTXSSPX
# CHECK-ALL: name: testSTXSSPX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTXSDX
# CHECK-ALL: name: testSTXSDX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTXVX
# CHECK-ALL: name: testSTXVX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSUBFC
# CHECK-ALL: name: testSUBFC
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSUBFC8
# CHECK-ALL: name: testSUBFC8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testXOR
# CHECK-ALL: name: testXOR
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testXOR8
# CHECK-ALL: name: testXOR8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testXORI
# CHECK-ALL: name: testXORI
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testXOR8I
# CHECK-ALL: name: testXOR8I
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testLXSSPX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTXSSPX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: testSTXSDX
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testExpandISEL
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: main
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: fn1
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
registers:
...
---
name: copycrunset
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: t1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: t2
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: t3
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: t4
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: t5
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: t6
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: t7
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: t8
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: t9
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: t10
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: LIS8
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: LIS
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: modify_and_kill_the_reg_in_the_same_inst
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: dead_load_immediate_followed_by_a_redundancy
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: test
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
name: testRLWINMSingleUseDef
# CHECK: testRLWINMSingleUseDef
# CHECK-LATE: testRLWINMSingleUseDef
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testRLWINMNoGPRUseZero
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testRLWINMNoGPRUseNonZero
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testRLDICLSingleUseDef
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testRLDICLNoGPRUseZero
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testRLDICLNoGPRUseNonZero
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: func
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: func
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: func
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: shrinkwrapme
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: tls_func
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: tls_func
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# in the middle. Because the non-select depends on the result of a previous
# select, we cannot optimize the sequence to share control-flow.
name: cmov_interleaved_bad
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
# the tail basic block, while debug info associated with non-selects is left
# in the head basic block.
name: cmov_interleaved_debug_value
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
# CHECK: id: 114, class
---
name: autogen_SD21418
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: vr128bit }
define void @encode_one_macroblock() { ret void }
---
name: encode_one_macroblock
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: addr64bit }
---
name: fun
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: gr32bit }
---
name: main
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: gr64bit }
---
name: fun1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: grx32bit }
---
name: fun
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64bit }
...
---
name: put_charge_groups_in_box
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
...
---
name: f1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$r2d' }
...
---
name: fun
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32bit }
...
---
name: Fun
-alignment: 4
+alignment: 16
tracksRegLiveness: true
...
---
name: f0
-alignment: 2
+alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: addr64bit }
---
name: proofnumberscan
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: addr64bit }
---
name: Perl_do_sv_dump
-alignment: 4
+alignment: 16
tracksRegLiveness: true
body: |
bb.0 :
...
---
name: LearnStoreTT
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$r2d' }
...
---
name: main
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: grx32bit }
# PR33677
---
name: main
-alignment: 2
+alignment: 4
tracksRegLiveness: true
# CHECK: $r0l = COPY renamable $r1l
# Although R0L partially redefines R0Q, it must not mark R0Q as kill
# PR40215.
---
name: main
-alignment: 4
+alignment: 16
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
...
---
name: func_32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$r2d', virtual-reg: '%10' }
---
name: main
-alignment: 4
+alignment: 16
tracksRegLiveness: true
body: |
bb.0:
...
---
name: foo4
-alignment: 1
+alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '$r0' }
...
---
name: jump_table
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: do_copy
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: size_limit
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: massive
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: size_limit
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: skip_spill
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: mov_between_dec_end
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: skip_spill
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: mov_between_dec_end
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: header_not_target_unrolled_loop
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: non_loop
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: ne_trip_count
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: size_limit
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: search
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: size_limit
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: copy
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_vminnmq_m_f32_v2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_vminnmq_m_f32_v2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_vminnmq_m_f32_v2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_vminnmq_m_f32_v2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_vminnmq_m_f32_v2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_vminnmq_m_f32_v2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_vminnmq_m_f32_v2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_vminnmq_m_f32_v2
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: vpnot
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
...
---
name: vpnot_end
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
...
---
name: vpnot_two
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
...
---
name: vpnot_lots
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
...
---
name: vpnot_first
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
...
---
name: vpnot_many
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
...
---
name: Func
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_check_type
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_add_v16i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v8i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v4i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v2i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v32i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v16i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v8i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v4i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v64i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v32i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v16i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v8i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_v64i8_2
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
---
name: test_add_i1
# CHECK-LABEL: name: test_add_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_add_i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_and_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_and_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_and_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_and_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_and_i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_ashr
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_ashr_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
---
name: test
# ALL-LABEL: name: test
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_cmp_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_cmp_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_cmp_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_cmp_i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_cmp_p0
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i1toi8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i1toi16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i8toi16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_zext_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i1toi8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i1toi16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i8toi16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sext_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i1toi8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i1toi16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i8toi16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_anyext_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_fadd_float
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_fadd_double
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_fdiv_float
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_fdiv_double
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_fmul_float
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_fmul_double
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_fptrunc
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_fsub_float
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_fsub_double
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
---
name: test_insert_128
# ALL-LABEL: name: test_insert_128
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_insert_128
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_insert_256
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_lshr
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_lshr_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
---
name: test_memop_s8tos32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
body: |
...
---
name: test_memop_s64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
liveins:
---
name: test_memop_s8tos32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
body: |
...
---
name: test_memop_s64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
liveins:
...
---
name: test_mul_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_mul_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_mul_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_mul_i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
---
name: test_mul_v8i16
# ALL-LABEL: name: test_mul_v8i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
---
name: test_mul_v4i32
# ALL-LABEL: name: test_mul_v4i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
---
name: test_mul_v2i64
# ALL-LABEL: name: test_mul_v2i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
---
name: test_mul_v16i16
# ALL-LABEL: name: test_mul_v16i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
---
name: test_mul_v8i32
# ALL-LABEL: name: test_mul_v8i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
---
name: test_mul_v4i64
# ALL-LABEL: name: test_mul_v4i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
---
name: test_mul_v32i16
# ALL-LABEL: name: test_mul_v32i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
---
name: test_mul_v16i32
# ALL-LABEL: name: test_mul_v16i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
---
name: test_mul_v8i64
# ALL-LABEL: name: test_mul_v8i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
...
---
name: test_or_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_or_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_or_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_or_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_or_i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_float
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_double
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_shl
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_shl_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_sub_v16i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v8i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v4i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v2i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v32i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v16i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v8i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v4i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v64i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v32i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v16i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_v8i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_sub_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_xor_i1
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_xor_i8
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_xor_i16
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_xor_i32
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
...
---
name: test_xor_i64
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
registers:
---
name: test_mul_vec256
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_add_vec256
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_sub_vec256
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
---
name: test_load_v8i32_noalign
# CHECK-LABEL: name: test_load_v8i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
---
name: test_store_v8i32_noalign
# CHECK-LABEL: name: test_store_v8i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
---
name: test_mul_vec512
# CHECK-LABEL: name: test_mul_vec512
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
---
name: test_add_vec512
# CHECK-LABEL: name: test_add_vec512
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
---
name: test_sub_vec512
# CHECK-LABEL: name: test_sub_vec512
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
name: test_load_v16i32_noalign
# CHECK-LABEL: name: test_load_v16i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
---
name: test_store_v16i32_noalign
# CHECK-LABEL: name: test_store_v16i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
---
name: test_uadde_i32
# CHECK-LABEL: name: test_uadde_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
...
---
name: test_add_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_add_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_add_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_add_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_mul_gpr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_add_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_add_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_fsub_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_fmul_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_fdiv_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_add_v4i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_add_v4f32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_load_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_load_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_load_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_load_i64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: false
...
---
name: test_load_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_load_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_load_v4i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_store_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_store_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_store_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: test_store_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
selected: false
...
---
name: constInt_check
-alignment: 4
+alignment: 16
legalized: true
registers:
- { id: 0, class: _ }
...
---
name: trunc_check
-alignment: 4
+alignment: 16
legalized: true
registers:
- { id: 0, class: _ }
...
---
name: test_icmp_eq_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_icmp_eq_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_icmp_eq_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_icmp_eq_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_xor_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_or_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_and_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_and_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_global_ptrv
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_undef
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_undef2
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_undef3
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_undef4
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
tracksRegLiveness: true
...
---
name: test_fpext
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: false
registers:
...
---
name: test_fptrunc
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: int32_to_float
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: int64_to_float
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: int32_to_double
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: int64_to_double
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: float_to_int8
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: float_to_int16
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: float_to_int32
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: float_to_int64
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: double_to_int8
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: double_to_int16
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: double_to_int32
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: double_to_int64
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_oeq
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_ogt
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_oge
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_olt
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_ole
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_one
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_ord
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_uno
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_ueq
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_ugt
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_uge
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_ult
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_ule
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_float_une
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_oeq
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_ogt
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_oge
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_olt
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_ole
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_one
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_ord
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_uno
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_ueq
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_ugt
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_uge
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_ult
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_ule
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
...
---
name: fcmp_double_une
-alignment: 4
+alignment: 16
legalized: true
tracksRegLiveness: true
registers:
---
name: test_global_ptrv
# CHECK-LABEL: name: test_global_ptrv
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
---
name: test_global_valv
# CHECK-LABEL: name: test_global_valv
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32ALL: registers:
---
name: test_global_ptrv
# CHECK-LABEL: name: test_global_ptrv
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X64ALL: registers:
---
name: test_global_valv
# CHECK-LABEL: name: test_global_valv
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X64ALL: registers:
---
name: test_add_v16i8
# ALL-LABEL: name: test_add_v16i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
---
name: test_add_v8i16
# ALL-LABEL: name: test_add_v8i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
---
name: test_add_v4i32
# ALL-LABEL: name: test_add_v4i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
---
name: test_add_v2i64
# ALL-LABEL: name: test_add_v2i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
---
name: test_add_v32i8
# ALL-LABEL: name: test_add_v32i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
---
name: test_add_v16i16
# ALL-LABEL: name: test_add_v16i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
---
name: test_add_v8i32
# ALL-LABEL: name: test_add_v8i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
---
name: test_add_v4i64
# ALL-LABEL: name: test_add_v4i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
...
---
name: test_add_v64i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_add_v32i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_add_v16i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_add_v8i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_add_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_add_i16
# ALL-LABEL: name: test_add_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
---
name: test_add_i8
# ALL-LABEL: name: test_add_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
---
name: test_add_v4i32
# ALL-LABEL: name: test_add_v4i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
---
name: test_add_v4f32
# ALL-LABEL: name: test_add_v4f32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
...
---
name: test_and_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_and_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_and_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_and_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_ashr_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i64_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i64_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i32_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i32_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i16_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i16_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i8_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_ashr_i8_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: test_blsi32rr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_blsi32rr_nomatch
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_blsr32rr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_blsr32rr_nomatch
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: uncondbr
# CHECK-LABEL: name: uncondbr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# CHECK: JMP_1 %bb.2
---
name: test
# CHECK-LABEL: name: test
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_eq_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_eq_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_eq_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_eq_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_ne_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_ugt_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_uge_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_ult_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_ule_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_sgt_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_sge_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_slt_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_icmp_sle_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: const_i64_u32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
...
---
name: main
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_copy
# ALL-LABEL: name: test_copy
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_copy2
# ALL-LABEL: name: test_copy2
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_copy3
# ALL-LABEL: name: test_copy3
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_copy4
# ALL-LABEL: name: test_copy4
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_copy5
# ALL-LABEL: name: test_copy5
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_copy6
# ALL-LABEL: name: test_copy6
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
...
---
name: test_zext_i1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_sext_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_sext_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: anyext_s64_from_s1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: anyext_s64_from_s8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: anyext_s64_from_s16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: anyext_s64_from_s32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_zext_i1toi8
# ALL-LABEL: name: test_zext_i1toi8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
---
name: test_zext_i1toi16
# ALL-LABEL: name: test_zext_i1toi16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
---
name: test_zext_i1
# ALL-LABEL: name: test_zext_i1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
---
name: test_zext_i8
# ALL-LABEL: name: test_zext_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_zext_i16
# ALL-LABEL: name: test_zext_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_sext_i8
# ALL-LABEL: name: test_sext_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_sext_i16
# ALL-LABEL: name: test_sext_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_anyext_i1toi8
# ALL-LABEL: name: test_anyext_i1toi8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
---
name: test_anyext_i1toi16
# ALL-LABEL: name: test_anyext_i1toi16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
---
name: test_anyext_i1toi32
# ALL-LABEL: name: test_anyext_i1toi32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
---
name: test_anyext_i8toi16
# ALL-LABEL: name: test_anyext_i8toi16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
---
name: test_anyext_i8toi32
# ALL-LABEL: name: test_anyext_i8toi32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
---
name: test_anyext_i16toi32
# ALL-LABEL: name: test_anyext_i16toi32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_extract_128_idx0
# ALL-LABEL: name: test_extract_128_idx0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# AVX: registers:
---
name: test_extract_128_idx1
# ALL-LABEL: name: test_extract_128_idx1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# AVX: registers:
---
name: test_extract_128_idx0
# ALL-LABEL: name: test_extract_128_idx0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_extract_128_idx1
# ALL-LABEL: name: test_extract_128_idx1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_extract_256_idx0
# ALL-LABEL: name: test_extract_256_idx0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
---
name: test_extract_256_idx1
# ALL-LABEL: name: test_extract_256_idx1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
...
---
name: test_fadd_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
...
---
name: test_fadd_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
---
name: test_float
#
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: test_double
#
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_fdiv_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
...
---
name: test_fdiv_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
...
---
name: test_fmul_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
...
---
name: test_fmul_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
...
---
name: test
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_fptrunc
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_fsub_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
...
---
name: test_fsub_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
...
---
name: test_gep_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
---
name: test_insert_128_idx0
# ALL-LABEL: name: test_insert_128_idx0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_insert_128_idx0_undef
# ALL-LABEL: name: test_insert_128_idx0_undef
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_insert_128_idx1
# ALL-LABEL: name: test_insert_128_idx1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_insert_128_idx1_undef
# ALL-LABEL: name: test_insert_128_idx1_undef
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_insert_128_idx0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_insert_128_idx0_undef
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_insert_128_idx1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_insert_128_idx1_undef
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_insert_256_idx0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_insert_256_idx0_undef
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_insert_256_idx1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_insert_256_idx1_undef
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_lshr_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i64_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i64_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i32_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i32_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i16_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i16_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i8_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_lshr_i8_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_load_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_float_vecreg
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_double_vecreg
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_float_vec
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_double_vec
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_ptr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
...
---
name: test_store_ptr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
...
---
name: test_gep_folding
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_gep_folding_largeGepIndex
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_ptr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_ptr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_float_vecreg
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_double_vecreg
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_float_vec
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_double_vec
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_ptr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
...
---
name: test_store_ptr
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
...
---
name: test_gep_folding
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_gep_folding_largeGepIndex
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
# ALL-LABEL: name: test_load_v4i32_noalign
name: test_load_v4i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
# ALL-LABEL: name: test_load_v4i32_align
name: test_load_v4i32_align
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
# ALL-LABEL: name: test_store_v4i32_align
name: test_store_v4i32_align
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
# ALL-LABEL: name: test_store_v4i32_noalign
name: test_store_v4i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_load_v8i32_noalign
# ALL-LABEL: name: test_load_v8i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
---
name: test_load_v8i32_align
# ALL-LABEL: name: test_load_v8i32_align
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_store_v8i32_noalign
# ALL-LABEL: name: test_store_v8i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
---
name: test_store_v8i32_align
# ALL-LABEL: name: test_store_v8i32_align
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
...
---
name: test_load_v16i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_load_v16i32_align
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_v16i32_noalign
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_store_v16i32_align
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_merge
#
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
...
---
name: test_merge_v128
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_merge_v256
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v8i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v8i16_avx
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v8i16_avx512bwvl
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v4i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v4i32_avx
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v4i32_avx512vl
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v2i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v16i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v16i16_avx512bwvl
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v8i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v8i32_avx512vl
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v4i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v32i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v16i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_mul_v8i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_or_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_or_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_or_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_or_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i64_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i64_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i32_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i32_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i16_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i16_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i8_imm
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_shl_i8_imm1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: test_sub_v16i8
# ALL-LABEL: name: test_sub_v16i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_sub_v8i16
# ALL-LABEL: name: test_sub_v8i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_sub_v4i32
# ALL-LABEL: name: test_sub_v4i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_sub_v2i64
# ALL-LABEL: name: test_sub_v2i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_sub_v32i8
# ALL-LABEL: name: test_sub_v32i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_sub_v16i16
# ALL-LABEL: name: test_sub_v16i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_sub_v8i32
# ALL-LABEL: name: test_sub_v8i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_sub_v4i64
# ALL-LABEL: name: test_sub_v4i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_sub_v64i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_sub_v32i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_sub_v16i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_sub_v8i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_sub_v4i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
...
---
name: test_sub_v4f32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
selected: false
...
---
name: trunc_i32toi1
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: trunc_i32toi8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: trunc_i32toi16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: trunc_i64toi8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: trunc_i64toi16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: trunc_i64toi32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test2
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test3
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
---
name: test_unmerge
#
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
#
...
---
name: test_unmerge_v128
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_unmerge_v256
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_xor_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_xor_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_xor_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
...
---
name: test_xor_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
registers:
---
name: test_global_ptrv
# ALL-LABEL: name: test_global_ptrv
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
...
---
name: inttoptr_p0_s32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: ptrtoint_s1_p0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: ptrtoint_s8_p0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: ptrtoint_s16_p0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: ptrtoint_s32_p0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_sdiv_i8
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_sdiv_i16
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_sdiv_i32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_srem_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_srem_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_srem_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_udiv_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_udiv_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_udiv_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_urem_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_urem_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_urem_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: inttoptr_p0_s32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint_s1_p0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint_s8_p0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint_s16_p0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint_s32_p0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_sdiv_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_sdiv_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_sdiv_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_srem_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_srem_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_srem_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: trap
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_udiv_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_udiv_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_udiv_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_urem_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_urem_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_urem_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
---
name: test_global_ptrv
# ALL-LABEL: name: test_global_ptrv
-alignment: 4
+alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
...
---
name: fcmp_float_oeq
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_ogt
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_oge
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_olt
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_ole
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_one
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_ord
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_uno
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_ueq
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_ugt
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_uge
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_ult
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_ule
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_une
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_oeq
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_ogt
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_oge
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_olt
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_ole
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_one
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_ord
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_uno
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_ueq
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_ugt
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_uge
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_ult
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_ule
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_double_une
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: float_to_int8
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: float_to_int16
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: float_to_int32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: float_to_int64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: double_to_int8
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: double_to_int16
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: double_to_int32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: double_to_int64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: inttoptr_p0_s64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: ptrtoint_s1_p0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: ptrtoint_s8_p0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: ptrtoint_s16_p0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: ptrtoint_s32_p0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: ptrtoint_s64_p0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_sdiv_i8
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_sdiv_i16
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_sdiv_i32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_sdiv_i64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: int8_to_float
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: int16_to_float
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: int32_to_float
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: int64_to_float
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: int8_to_double
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: int16_to_double
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: int32_to_double
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: int64_to_double
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: test_srem_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_srem_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_srem_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_srem_i64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_udiv_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_udiv_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_udiv_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_udiv_i64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_urem_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_urem_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_urem_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_urem_i64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: zext_i1_to_i8
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: zext_i1_to_i16
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: zext_i1_to_i32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: zext_i1_to_i64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: zext_i8_to_i16
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: zext_i8_to_i32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: zext_i8_to_i64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: zext_i16_to_i32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: zext_i16_to_i64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: zext_i32_to_i64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
...
---
name: fcmp_float_oeq
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_ogt
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_oge
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_olt
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_ole
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_one
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_ord
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_uno
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_ueq
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_ugt
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_uge
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_ult
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_ule
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_float_une
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_oeq
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_ogt
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_oge
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_olt
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_ole
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_one
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_ord
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_uno
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_ueq
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_ugt
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_uge
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_ult
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_ule
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: fcmp_double_une
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_to_int8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_to_int16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_to_int32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: float_to_int64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_to_int8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_to_int16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_to_int32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: double_to_int64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: inttoptr_p0_s64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint_s1_p0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint_s8_p0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint_s16_p0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint_s32_p0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: ptrtoint_s64_p0
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_sdiv_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_sdiv_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_sdiv_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_sdiv_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: int32_to_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: int64_to_float
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: int32_to_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: int64_to_double
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: test_srem_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_srem_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_srem_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_srem_i64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_udiv_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_udiv_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_udiv_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_udiv_i64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_urem_i8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_urem_i16
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_urem_i32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: test_urem_i64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: true
regBankSelected: true
...
---
name: zext_i1_to_i8
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zext_i1_to_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zext_i1_to_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zext_i1_to_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zext_i8_to_i16
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zext_i8_to_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zext_i8_to_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zext_i16_to_i32
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zext_i16_to_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: zext_i32_to_i64
-alignment: 4
+alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
...
---
name: foo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: adcx32_commute
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: adcx64_commute
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: adox32_commute
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: adox64_commute
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: debug
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: nodebug
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: debug
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: debug
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_imm_store
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
...
---
name: test_offset
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: main
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
# CHECK-LABEL: or:
name: or
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
---
# CHECK-LABEL: and:
name: and
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
---
# CHECK: name: f
name: f
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
...
---
name: f
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: bb.12.for.body.10
name: _Z3fn1v
-alignment: 4
+alignment: 16
tracksRegLiveness: true
constants:
body: |
...
---
name: test_fcmp_storefloat
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_8bitops
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_16bitops
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_32bitops
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_64bitops
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_16bitext
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_32bitext
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_64bitext
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
# CHECK-LABEL: name: test1
name: test1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rax' }
---
# CHECK-LABEL: name: test2
name: test2
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rax' }
---
# CHECK-LABEL: name: test3
name: test3
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
---
# CHECK-LABEL: name: test4
name: test4
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$r9d' }
---
# CHECK-LABEL: name: test5
name: test5
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$ch', reg: '$bl' }
---
name: imp_null_check_with_bitwise_op_0
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_0
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
...
---
name: imp_null_check_with_bitwise_op_1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
---
name: imp_null_check_with_bitwise_op_2
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_2
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
---
name: imp_null_check_with_bitwise_op_3
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_3
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
---
name: imp_null_check_with_bitwise_op_4
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_4
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
---
name: no_hoist_across_call
# CHECK-LABEL: name: no_hoist_across_call
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# an implicit null check -- hoisting it will require hosting the move
# to $esi and we cannot do that without clobbering the use of $rsi in
# the first instruction in bb.1.not_null.
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JMP_1 %bb.1
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK: bb.0.entry:
# CHECK: $eax = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg, implicit-def $rax :: (load 4 from %ir.x)
# CHECK-NEXT: JMP_1 %bb.1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK: $rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags
# CHECK-NEXT: $esi = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $esi, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
# CHECK-NEXT: JMP_1 %bb.1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JMP_1 %bb.1
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JMP_1 %bb.1
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JMP_1 %bb.1
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JMP_1 %bb.1
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JMP_1 %bb.1
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JMP_1 %bb.1
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
-alignment: 4
+alignment: 16
tracksRegLiveness: true
stack:
- { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8}
# that clobber the register used in TEST.
name: reg-rewrite
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
...
---
name: _Z3fooi
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: fn1
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test2add_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test2add_ebp_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1add_ebp_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_ebp_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1lea_ebp_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test2addi32_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1mov1add_ebp_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_ebp_index_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_ebp_index2_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_skip_opt_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_skip_eflags_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_64_32_1
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_rbp_64_32_1
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1lea_rbp_64_32_1
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test2add_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test2add_rbp_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1add_rbp_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_64_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_rbp_64_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1lea_rbp_64_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_rbp_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1lea_rbp_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test8
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaaddi32_64_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1mov1add_rbp_64_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_rbp_index_64_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_rbp_index2_64_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test2addi32_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test1mov1add_rbp_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_rbp_index_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: testleaadd_rbp_index2_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_skip_opt_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_skip_eflags_64
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_skip_opt_64_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: test_skip_eflags_64_32
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z3fooi
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
# CHECK-NEXT: ADJCALLSTACKUP32 20, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
# CHECK-NEXT: RET 0
name: test9
-alignment: 0
+alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...\r
---\r
name: eggs\r
-alignment: 4\r
+alignment: 16\r
tracksRegLiveness: true\r
fixedStack: \r
- { id: 0, type: spill-slot, offset: -56, size: 8, alignment: 8, callee-saved-register: '$rbx' }\r
...
---
name: test
-alignment: 4
+alignment: 16
tracksRegLiveness: true
jumpTable:
kind: block-address
...
---
name: atomic
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
...
---
name: nonatomic_unoptimized
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
# CHECK-NEXT: DBG_VALUE $eax,
# CHECK: bb.2:
name: x1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
body: |
bb.0:
...
---
name: main
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: main
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: JCC_1 %[[L1]], 5
name: foo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK: hints: $ebx $edi
# CHECK-NOT: hints: $ebx $edi $ebx $edi
name: fun
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: '@shrink_wrap_basic@16'
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
---
name: bar
# CHECK-LABEL: name: bar
-alignment: 4
+alignment: 16
tracksRegLiveness: true
body: |
bb.0:
...
---
name: stack_fold_adcx32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: stack_fold_adcx64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: stack_fold_adox32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: stack_fold_adox64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: stack_fold_mulx_u32
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
...
---
name: stack_fold_mulx_u64
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
name: main4k
# CHECK-LABEL: name: main4k
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
maxAlignment: 8
...
---
name: "\x01+[MyObject doWithSize:]"
-alignment: 2
+alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
...
---
name: asan.module_ctor
-alignment: 2
+alignment: 4
tracksRegLiveness: true
frameInfo:
stackSize: 16
---
# CHECK-LABEL: name: f1
name: f1
-alignment: 2
+alignment: 4
legalized: true
regBankSelected: true
selected: true
...
---
name: _ZN1BC2Ev
-alignment: 1
+alignment: 2
liveins:
- { reg: '$r0' }
frameInfo:
...
---
name: _ZN1BC1Ev
-alignment: 1
+alignment: 2
liveins:
- { reg: '$r0' }
frameInfo:
...
---
name: f
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _ZN1v2bvEv
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: f
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: f
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: f
-alignment: 1
+alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 2
+alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 3
+alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$edi' }
...
---
name: fn1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
...
---
name: f
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 4
+alignment: 16
frameInfo:
stackSize: 24
offsetAdjustment: -24
...
---
name: fn1
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins: []
body: |
...
---
name: '$S4main1fyyF'
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _ZN1C5m_fn3Ev
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: add
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
...
---
name: foo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: baaar
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
...
---
name: f
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
# CHECK-NEXT: DBG_VALUE $rbx, $noreg, ![[QVAR]], !DIExpression(DW_OP_LLVM_fragment, 32, 32)
name: g
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
# CHECK: DBG_VALUE $rdi, $noreg, ![[RVAR]], !DIExpression(DW_OP_plus_uconst, 1)
name: h
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
# CHECK: DBG_VALUE $rsp, 0, ![[SVAR]], !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_plus_uconst, 1)
# CHECK: DBG_VALUE $rdi, $noreg, ![[SVAR]], !DIExpression(DW_OP_plus_uconst, 1)
name: i
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
...
---
name: foo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: main
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
...
---
name: main
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: main
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: f
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: bar
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
...
---
name: Process
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: foo
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$edi' }
...
---
name: foo
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: main
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
maxAlignment: 4
...
---
name: main
-alignment: 4
+alignment: 16
registers:
- { id: 0, class: gr32, preferred-register: '' }
body: |
...
---
name: _Z3bari
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$edi' }
# Checking that we have two compile units with two sets of high/lo_pc.
# CHECK: .debug_info contents
# CHECK: DW_TAG_compile_unit
-# CHECK: DW_AT_low_pc {{.*}} (0x0000000000000018 ".text")
+# CHECK: DW_AT_low_pc {{.*}} (0x0000000000000020 ".text")
# CHECK: DW_AT_high_pc
#
# CHECK: DW_TAG_subprogram
# CHECK: DW_TAG_formal_parameter
# CHECK-NOT: DW_TAG
# CHECK: DW_AT_location [DW_FORM_sec_offset] ({{.*}}
-# CHECK-NEXT: [0x00000021, 0x0000002f): DW_OP_breg0 EAX+0, DW_OP_deref
-# CHECK-NEXT: [0x0000002f, 0x0000005b): DW_OP_breg5 EBP-8, DW_OP_deref, DW_OP_deref
+# CHECK-NEXT: [0x00000029, 0x00000037): DW_OP_breg0 EAX+0, DW_OP_deref
+# CHECK-NEXT: [0x00000037, 0x00000063): DW_OP_breg5 EBP-8, DW_OP_deref, DW_OP_deref
# CHECK-NEXT: DW_AT_name [DW_FORM_strp]{{.*}}"a"
#
# CHECK: DW_TAG_variable
...
---
name: _Z3bari
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
stackSize: 8
...
---
name: _Z3baz1A
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
stackSize: 28
...
---
name: f
-alignment: 4
+alignment: 16
tracksRegLiveness: true
frameInfo:
stackSize: 24
...
---
name: foo
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers: []
liveins:
...
---
name: bar
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers: []
liveins:
...
---
name: baz
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers: []
liveins:
...
---
name: qux
-alignment: 4
+alignment: 16
tracksRegLiveness: true
registers: []
liveins:
...
---
name: f
-alignment: 4
+alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
...
---
name: _Z11parse_rangeRyS_Ss
-alignment: 4
+alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }