dev_err(aml_chip->chip.dev,
"enable,index is not legal\n");
return -EINVAL;
-
- break;
}
pwm_set_reg_bits(&aml_reg->miscr, val, val);
dev_err(aml_chip->chip.dev,
"enable,index is not legal\n");
return -EINVAL;
- break;
}
pwm_set_reg_bits(&aml_reg->miscr, val, val);
case PWM_AO_A2:
case PWM_AO_C2:
val = 0 << 25;
- mask = 25 << 1;
+ mask = 1 << 25;
break;
case PWM_B2:
case PWM_D2:
case PWM_AO_B2:
case PWM_AO_D2:
val = 0 << 24;
- mask = 24 << 1;
+ mask = 1 << 24;
break;
default:
val = 0 << 0;
dev_err(aml_chip->chip.dev,
"config_ext,index is not legal\n");
return -EINVAL;
-
- break;
}
pwm_set_reg_bits(&aml_reg->miscr, clk_source_mask, clk_source_val);
pwm_set_reg_bits(&aml_reg->miscr, clk_mask, clk_val);
if (IS_ERR(chip->baseaddr.cd_base))
return PTR_ERR(chip->baseaddr.cd_base);
- chip->baseaddr.aoab_base = of_iomap(np, 3);
+ chip->baseaddr.aoab_base = of_iomap(np, 2);
if (IS_ERR(chip->baseaddr.aoab_base))
return PTR_ERR(chip->baseaddr.aoab_base);
- chip->baseaddr.aocd_base = of_iomap(np, 4);
+ chip->baseaddr.aocd_base = of_iomap(np, 3);
if (IS_ERR(chip->baseaddr.aocd_base))
return PTR_ERR(chip->baseaddr.aocd_base);
dev_err(aml_chip->chip.dev,
"enable,index is not legal\n");
return -EINVAL;
- break;
}
pwm_set_reg_bits(&aml_reg->miscr, val, val);
dev_err(aml_chip->chip.dev,
"constant disable,index is not legal\n");
return -EINVAL;
-
- break;
}
pwm_set_reg_bits(&aml_reg->miscr, mask, val);
return 0;
case PWM_AO_C:
clear_val = 0xff << 24;
val = value << 24;
+ break;
case PWM_B:
case PWM_D:
case PWM_F:
case PWM_AO_C2:
clear_val = 0xff << 16;
val = value << 16;
+ break;
case PWM_B2:
case PWM_D2:
case PWM_F2:
dev_err(aml_chip->chip.dev,
"times,index is not legal\n");
return -EINVAL;
-
- break;
}
pwm_clear_reg_bits(&aml_reg->tr, clear_val);
pwm_write_reg1(&aml_reg->tr, val);
case PWM_AO_A:
case PWM_AO_C:
val = 1 << 8;
+ break;
case PWM_B:
case PWM_D:
case PWM_F:
case PWM_AO_B:
case PWM_AO_D:
val = 1 << 9;
+ break;
default:
dev_err(aml_chip->chip.dev,
"blink enable,index is not legal\n");
return -EINVAL;
- break;
}
pwm_set_reg_bits(&aml_reg->br, val, val);
case PWM_AO_C:
mask = 1 << 8;
val = 0 << 8;
+ break;
case PWM_B:
case PWM_D:
case PWM_F:
case PWM_AO_D:
mask = 1 << 9;
val = 0 << 9;
+ break;
default:
dev_err(aml_chip->chip.dev,
"blink enable,index is not legal\n");
return -EINVAL;
- break;
}
pwm_set_reg_bits(&aml_reg->br, mask, val);
case PWM_AO_C:
clear_val = 0xf;
val = value;
+ break;
case PWM_B:
case PWM_D:
case PWM_F:
dev_err(aml_chip->chip.dev,
"times,index is not legal\n");
return -EINVAL;
- break;
}
- pwm_clear_reg_bits(&aml_reg->tr, clear_val);
- pwm_write_reg1(&aml_reg->tr, val);
+ pwm_clear_reg_bits(&aml_reg->br, clear_val);
+ pwm_write_reg1(&aml_reg->br, val);
return 0;
}
case PWM_AO_D:
case PWM_AO_C2:
case PWM_AO_D2:
- baseaddr = aml_chip->baseaddr.aoab_base;
+ baseaddr = aml_chip->baseaddr.aocd_base;
break;
default:
pr_err("unknown pwm id: %d\n", pwm_id);
#define PWM_B 1
#define PWM_C 2
#define PWM_D 3
-#define PWM_E 4
-#define PWM_F 5
-#define PWM_AO_A 6
-#define PWM_AO_B 7
+#define PWM_AO_A 4
+#define PWM_AO_B 5
+#define PWM_AO_C 6
+#define PWM_AO_D 7
/*
* Addtional 8 channels for gxtvbb , gxl ,gxm and txl
#define PWM_B2 9
#define PWM_C2 10
#define PWM_D2 11
-#define PWM_E2 12
-#define PWM_F2 13
-#define PWM_AO_A2 14
-#define PWM_AO_B2 15
+#define PWM_AO_A2 12
+#define PWM_AO_B2 13
+#define PWM_AO_C2 14
+#define PWM_AO_D2 15
/*add another four channels for txlx*/
-#define PWM_AO_C 16
-#define PWM_AO_D 17
-#define PWM_AO_C2 18
-#define PWM_AO_D2 19
+#define PWM_E 16
+#define PWM_F 17
+#define PWM_E2 18
+#define PWM_F2 19
+
+
+
#define CLKID_PLL_VID_NOT /*for gxl gxm not support it*/
PWM_B,
PWM_C,
PWM_D,
- PWM_E,
- PWM_F,
PWM_AO_A,
PWM_AO_B,
+ PWM_AO_C,
+ PWM_AO_D,
PWM_A2,
PWM_B2,
PWM_C2,
PWM_D2,
- PWM_E2,
- PWM_F2,
PWM_AO_A2,
PWM_AO_B2,
- /* add another four channels for txlx*/
- PWM_AO_C,
- PWM_AO_D,
PWM_AO_C2,
PWM_AO_D2,
+ /* add another four channels for txlx*/
+ PWM_E,
+ PWM_F,
+ PWM_E2,
+ PWM_F2,
+
+
};
/*pwm att*/