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ARM: mx5: Enable L2 cache
author
Fabio Estevam
<fabio.estevam@freescale.com>
Mon, 30 Sep 2013 16:16:52 +0000
(13:16 -0300)
committer
Stefano Babic
<sbabic@denx.de>
Thu, 31 Oct 2013 16:54:03 +0000
(17:54 +0100)
Enable L2 cache for improving the system performance.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
arch/arm/cpu/armv7/mx5/lowlevel_init.S
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diff --git
a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index
25fadf6
..
97077fd
100644
(file)
--- a/
arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/
arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@
-45,6
+45,12
@@
#endif
mcr 15, 1, r0, c9, c0, 2
+
+ /* enable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #2
+ mcr 15, 0, r0, c1, c0, 1
+
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.