mv_ddr: ddr3: Update {min,max}_read_sample calculation

Measurements on actual hardware shown that the read ODT is early by 3
clocks. Adjust the calculation to avoid this.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
index ce9a47f..58ffb20 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
@@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
                        min_read_sample = read_sample[cs_num];
        }
 
-       min_read_sample = min_read_sample - 1;
-       max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
+       min_read_sample = min_read_sample + 2;
+       max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1;
        if (min_read_sample >= 0xf)
                min_read_sample = 0xf;
        if (max_read_sample >= 0x1f)