[gas/]

	* config/tc-mips.c (macro2): Implement rotates by zero using shifts
        by zero.

[gas/testsuite]
	* gas/mips/rol.s: Add rotate by zero tests.
	* gas/mips/rol.d: Update accordingly.
	* gas/mips/rol64.d: Expect rotates by zero to use dsrl.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b6d55a1..3f0462b 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2002-08-20  Richard Sandiford  <rsandifo@redhat.com>
+
+       * config/tc-mips.c (macro2): Implement rotates by zero using shifts
+       by zero.
+
 2002-08-19  Elena Zannoni  <ezannoni@redhat.com>
 
         From matthew green  <mrg@redhat.com>

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 771869c..4b78562 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -6653,22 +6653,27 @@ macro2 (ip)
     case M_DROL_I:
       {
        unsigned int rot;
-       char *l, *r;
 
        if (imm_expr.X_op != O_constant)
          as_bad (_("rotate count too large"));
        rot = imm_expr.X_add_number & 0x3f;
-       if (! rot)
-         break;
-       l = (rot < 0x20) ? "dsll" : "dsll32";
-       r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
-       rot &= 0x1f;
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
-                    "d,w,<", AT, sreg, rot);
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
-                    "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
-                    "d,v,t", dreg, dreg, AT);
+       if (rot == 0)
+         macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
+                      "d,w,<", dreg, sreg, 0);
+       else
+         {
+           char *l, *r;
+
+           l = (rot < 0x20) ? "dsll" : "dsll32";
+           r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
+           rot &= 0x1f;
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+                        "d,w,<", AT, sreg, rot);
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+                        "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+                        "d,v,t", dreg, dreg, AT);
+         }
       }
       break;
 
@@ -6679,14 +6684,18 @@ macro2 (ip)
        if (imm_expr.X_op != O_constant)
          as_bad (_("rotate count too large"));
        rot = imm_expr.X_add_number & 0x1f;
-       if (! rot)
-         break;
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
-                    "d,w,<", AT, sreg, rot);
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
-                    "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
-                    "d,v,t", dreg, dreg, AT);
+       if (rot == 0)
+         macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+                      "d,w,<", dreg, sreg, 0);
+       else
+         {
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+                        "d,w,<", AT, sreg, rot);
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+                        "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+                        "d,v,t", dreg, dreg, AT);
+         }
       }
       break;
 
@@ -6715,22 +6724,27 @@ macro2 (ip)
     case M_DROR_I:
       {
        unsigned int rot;
-       char *l, *r;
 
        if (imm_expr.X_op != O_constant)
          as_bad (_("rotate count too large"));
        rot = imm_expr.X_add_number & 0x3f;
-       if (! rot)
-         break;
-       r = (rot < 0x20) ? "dsrl" : "dsrl32";
-       l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
-       rot &= 0x1f;
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
-                    "d,w,<", AT, sreg, rot);
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
-                    "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
-                    "d,v,t", dreg, dreg, AT);
+       if (rot == 0)
+         macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
+                      "d,w,<", dreg, sreg, 0);
+       else
+         {
+           char *l, *r;
+
+           r = (rot < 0x20) ? "dsrl" : "dsrl32";
+           l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
+           rot &= 0x1f;
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
+                        "d,w,<", AT, sreg, rot);
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
+                        "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+                        "d,v,t", dreg, dreg, AT);
+         }
       }
       break;
 
@@ -6741,14 +6755,18 @@ macro2 (ip)
        if (imm_expr.X_op != O_constant)
          as_bad (_("rotate count too large"));
        rot = imm_expr.X_add_number & 0x1f;
-       if (! rot)
-         break;
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
-                    "d,w,<", AT, sreg, rot);
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
-                    "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
-       macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
-                    "d,v,t", dreg, dreg, AT);
+       if (rot == 0)
+         macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+                      "d,w,<", dreg, sreg, 0);
+       else
+         {
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
+                        "d,w,<", AT, sreg, rot);
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
+                        "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+           macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
+                        "d,v,t", dreg, dreg, AT);
+         }
       }
       break;
 

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index bce7c4a..539a6f6 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2002-08-20  Richard Sandiford  <rsandifo@redhat.com>
+
+       * gas/mips/rol.s: Add rotate by zero tests.
+       * gas/mips/rol.d: Update accordingly.
+       * gas/mips/rol64.d: Expect rotates by zero to use dsrl.
+
 2002-08-19  Elena Zannoni   <ezannoni@redhat.com>
 
         From  matthew green  <mrg@redhat.com>

diff --git a/gas/testsuite/gas/mips/rol.d b/gas/testsuite/gas/mips/rol.d
index 78f39f1..2128dd5 100644 (file)
--- a/gas/testsuite/gas/mips/rol.d
+++ b/gas/testsuite/gas/mips/rol.d
@@ -21,17 +21,20 @@ Disassembly of section .text:
 0+002c <[^>]*> sll     at,a1,0x1
 0+0030 <[^>]*> srl     a0,a1,0x1f
 0+0034 <[^>]*> or      a0,a0,at
-0+0038 <[^>]*> negu    at,a1
-0+003c <[^>]*> sllv    at,a0,at
-0+0040 <[^>]*> srlv    a0,a0,a1
-0+0044 <[^>]*> or      a0,a0,at
-0+0048 <[^>]*> negu    at,a2
-0+004c <[^>]*> sllv    at,a1,at
-0+0050 <[^>]*> srlv    a0,a1,a2
-0+0054 <[^>]*> or      a0,a0,at
-0+0058 <[^>]*> srl     at,a0,0x1
-0+005c <[^>]*> sll     a0,a0,0x1f
-0+0060 <[^>]*> or      a0,a0,at
-0+0064 <[^>]*> srl     at,a1,0x1
-0+0068 <[^>]*> sll     a0,a1,0x1f
-0+006c <[^>]*> or      a0,a0,at
+0+0038 <[^>]*> srl     a0,a1,0x0
+0+003c <[^>]*> negu    at,a1
+0+0040 <[^>]*> sllv    at,a0,at
+0+0044 <[^>]*> srlv    a0,a0,a1
+0+0048 <[^>]*> or      a0,a0,at
+0+004c <[^>]*> negu    at,a2
+0+0050 <[^>]*> sllv    at,a1,at
+0+0054 <[^>]*> srlv    a0,a1,a2
+0+0058 <[^>]*> or      a0,a0,at
+0+005c <[^>]*> srl     at,a0,0x1
+0+0060 <[^>]*> sll     a0,a0,0x1f
+0+0064 <[^>]*> or      a0,a0,at
+0+0068 <[^>]*> srl     at,a1,0x1
+0+006c <[^>]*> sll     a0,a1,0x1f
+0+0070 <[^>]*> or      a0,a0,at
+0+0074 <[^>]*> srl     a0,a1,0x0
+       ...

diff --git a/gas/testsuite/gas/mips/rol.s b/gas/testsuite/gas/mips/rol.s
index 259a957..988d702 100644 (file)
--- a/gas/testsuite/gas/mips/rol.s
+++ b/gas/testsuite/gas/mips/rol.s
@@ -5,8 +5,11 @@ foo:
        rol     $4,$5,$6
        rol     $4,1
        rol     $4,$5,1
+       rol     $4,$5,0
 
        ror     $4,$5
        ror     $4,$5,$6
        ror     $4,1
        ror     $4,$5,1
+       ror     $4,$5,0
+       .space  8

diff --git a/gas/testsuite/gas/mips/rol64.d b/gas/testsuite/gas/mips/rol64.d
index 8362219..32b132b 100644 (file)
--- a/gas/testsuite/gas/mips/rol64.d
+++ b/gas/testsuite/gas/mips/rol64.d
@@ -18,45 +18,49 @@ Disassembly of section .text:
 0+0020 <[^>]*> dsll    at,a0,0x1
 0+0024 <[^>]*> dsrl32  a0,a0,0x1f
 0+0028 <[^>]*> or      a0,a0,at
-0+002c <[^>]*> dsll    at,a1,0x1
-0+0030 <[^>]*> dsrl32  a0,a1,0x1f
-0+0034 <[^>]*> or      a0,a0,at
-0+0038 <[^>]*> dsll    at,a1,0x1f
-0+003c <[^>]*> dsrl32  a0,a1,0x1
-0+0040 <[^>]*> or      a0,a0,at
-0+0044 <[^>]*> dsll32  at,a1,0x0
-0+0048 <[^>]*> dsrl32  a0,a1,0x0
-0+004c <[^>]*> or      a0,a0,at
-0+0050 <[^>]*> dsll32  at,a1,0x1
-0+0054 <[^>]*> dsrl    a0,a1,0x1f
-0+0058 <[^>]*> or      a0,a0,at
-0+005c <[^>]*> dsll32  at,a1,0x1f
-0+0060 <[^>]*> dsrl    a0,a1,0x1
-0+0064 <[^>]*> or      a0,a0,at
-0+0068 <[^>]*> dnegu   at,a1
-0+006c <[^>]*> dsllv   at,a0,at
-0+0070 <[^>]*> dsrlv   a0,a0,a1
-0+0074 <[^>]*> or      a0,a0,at
-0+0078 <[^>]*> dnegu   at,a2
-0+007c <[^>]*> dsllv   at,a1,at
-0+0080 <[^>]*> dsrlv   a0,a1,a2
-0+0084 <[^>]*> or      a0,a0,at
-0+0088 <[^>]*> dsrl    at,a0,0x1
-0+008c <[^>]*> dsll32  a0,a0,0x1f
-0+0090 <[^>]*> or      a0,a0,at
-0+0094 <[^>]*> dsrl    at,a1,0x1
-0+0098 <[^>]*> dsll32  a0,a1,0x1f
-0+009c <[^>]*> or      a0,a0,at
-0+00a0 <[^>]*> dsrl    at,a1,0x1f
-0+00a4 <[^>]*> dsll32  a0,a1,0x1
+0+002c <[^>]*> dsrl    a0,a1,0x0
+0+0030 <[^>]*> dsll    at,a1,0x1
+0+0034 <[^>]*> dsrl32  a0,a1,0x1f
+0+0038 <[^>]*> or      a0,a0,at
+0+003c <[^>]*> dsll    at,a1,0x1f
+0+0040 <[^>]*> dsrl32  a0,a1,0x1
+0+0044 <[^>]*> or      a0,a0,at
+0+0048 <[^>]*> dsll32  at,a1,0x0
+0+004c <[^>]*> dsrl32  a0,a1,0x0
+0+0050 <[^>]*> or      a0,a0,at
+0+0054 <[^>]*> dsll32  at,a1,0x1
+0+0058 <[^>]*> dsrl    a0,a1,0x1f
+0+005c <[^>]*> or      a0,a0,at
+0+0060 <[^>]*> dsll32  at,a1,0x1f
+0+0064 <[^>]*> dsrl    a0,a1,0x1
+0+0068 <[^>]*> or      a0,a0,at
+0+006c <[^>]*> dsrl    a0,a1,0x0
+0+0070 <[^>]*> dnegu   at,a1
+0+0074 <[^>]*> dsllv   at,a0,at
+0+0078 <[^>]*> dsrlv   a0,a0,a1
+0+007c <[^>]*> or      a0,a0,at
+0+0080 <[^>]*> dnegu   at,a2
+0+0084 <[^>]*> dsllv   at,a1,at
+0+0088 <[^>]*> dsrlv   a0,a1,a2
+0+008c <[^>]*> or      a0,a0,at
+0+0090 <[^>]*> dsrl    at,a0,0x1
+0+0094 <[^>]*> dsll32  a0,a0,0x1f
+0+0098 <[^>]*> or      a0,a0,at
+0+009c <[^>]*> dsrl    a0,a1,0x0
+0+00a0 <[^>]*> dsrl    at,a1,0x1
+0+00a4 <[^>]*> dsll32  a0,a1,0x1f
 0+00a8 <[^>]*> or      a0,a0,at
-0+00ac <[^>]*> dsrl32  at,a1,0x0
-0+00b0 <[^>]*> dsll32  a0,a1,0x0
+0+00ac <[^>]*> dsrl    at,a1,0x1f
+0+00b0 <[^>]*> dsll32  a0,a1,0x1
 0+00b4 <[^>]*> or      a0,a0,at
-0+00b8 <[^>]*> dsrl32  at,a1,0x1
-0+00bc <[^>]*> dsll    a0,a1,0x1f
+0+00b8 <[^>]*> dsrl32  at,a1,0x0
+0+00bc <[^>]*> dsll32  a0,a1,0x0
 0+00c0 <[^>]*> or      a0,a0,at
-0+00c4 <[^>]*> dsrl32  at,a1,0x1f
-0+00c8 <[^>]*> dsll    a0,a1,0x1
+0+00c4 <[^>]*> dsrl32  at,a1,0x1
+0+00c8 <[^>]*> dsll    a0,a1,0x1f
 0+00cc <[^>]*> or      a0,a0,at
+0+00d0 <[^>]*> dsrl32  at,a1,0x1f
+0+00d4 <[^>]*> dsll    a0,a1,0x1
+0+00d8 <[^>]*> or      a0,a0,at
+0+00dc <[^>]*> dsrl    a0,a1,0x0
        ...