unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
- if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
- return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
-
if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
+ if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
+ return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
+ DAG);
+
return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
TargetMask, DAG);
}
ret <4 x float> %b
; CHECK: test1:
; CHECK: vshufps
-; CHECK: vpermilps
+; CHECK: vpshufd
}
; rdar://10538417
define <4 x float> @test12(<4 x float>* %a) nounwind {
; CHECK: test12
-; CHECK: vpermilps $27, (
+; CHECK: vpshufd
%tmp0 = load <4 x float>* %a
%tmp1 = shufflevector <4 x float> %tmp0, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x float> %tmp1
ret <8 x float> %tmp
}
-; CHECK: vpermilps $0
+; CHECK: vpshufd $0
; CHECK-NEXT: vinsertf128 $1
define <8 x float> @funcG(<8 x float> %a) nounwind uwtable readnone ssp {
entry:
}
; CHECK: vextractf128 $1
-; CHECK-NEXT: vpermilps $85
+; CHECK-NEXT: vpshufd
; CHECK-NEXT: vinsertf128 $1
define <8 x float> @funcH(<8 x float> %a) nounwind uwtable readnone ssp {
entry: