public:
/// Constructor for the mapping of an instruction.
- /// \p NumOperands should be equal to number of all the operands of
+ /// \p NumOperands must be equal to number of all the operands of
/// the related instruction.
/// The rationale is that it is more efficient for the optimizers
/// to be able to assume that the mapping of the ith operand is
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
void RegisterBankInfo::InstructionMapping::verify(
const MachineInstr &MI) const {
// Check that all the register operands are properly mapped.
+ const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+ // Check the constructor invariant.
+ assert(NumOperands == MI.getNumOperands() &&
+ "NumOperands must match, see constructor");
+ for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
+ const MachineOperand &MO = MI.getOperand(Idx);
+ const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
+ if (!MO.isReg()) {
+ assert(MOMapping.BreakDown.empty() &&
+ "We should not care about non-reg mapping");
+ continue;
+ }
+ unsigned Reg = MO.getReg();
+ // Register size in bits.
+ // This size must match what the mapping expect.
+ unsigned RegSize = MRI.getSize(Reg);
+ // If Reg is not a generic register, query the register class to
+ // get its size.
+ if (!RegSize)
+ RegSize = MRI.getRegClass(Reg)->getSize() * 8;
+ MOMapping.verify(RegSize);
+ }
}