drm/exynos: gsc: always use hw buffer 0 until queue management get fixed

Buffer sequence selection is broken and must be fixed. For the time being
always queue buffers for hw id 0, because hardware always operates on the
first src and dst buffer. This fixes IOMMU faults and makes the driver
usable from userspace.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index a8f53d5..e5cca9f 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -728,16 +728,16 @@ static int gsc_src_set_addr(struct device *dev,
        switch (buf_type) {
        case IPP_BUF_ENQUEUE:
                gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
-                       GSC_IN_BASE_ADDR_Y(buf_id));
+                       GSC_IN_BASE_ADDR_Y(0));
                gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
-                       GSC_IN_BASE_ADDR_CB(buf_id));
+                       GSC_IN_BASE_ADDR_CB(0));
                gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
-                       GSC_IN_BASE_ADDR_CR(buf_id));
+                       GSC_IN_BASE_ADDR_CR(0));
                break;
        case IPP_BUF_DEQUEUE:
-               gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));
-               gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));
-               gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));
+               gsc_write(0x0, GSC_IN_BASE_ADDR_Y(0));
+               gsc_write(0x0, GSC_IN_BASE_ADDR_CB(0));
+               gsc_write(0x0, GSC_IN_BASE_ADDR_CR(0));
                break;
        default:
                /* bypass */
@@ -1176,16 +1176,16 @@ static int gsc_dst_set_addr(struct device *dev,
        switch (buf_type) {
        case IPP_BUF_ENQUEUE:
                gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
-                       GSC_OUT_BASE_ADDR_Y(buf_id));
+                       GSC_OUT_BASE_ADDR_Y(0));
                gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
-                       GSC_OUT_BASE_ADDR_CB(buf_id));
+                       GSC_OUT_BASE_ADDR_CB(0));
                gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
-                       GSC_OUT_BASE_ADDR_CR(buf_id));
+                       GSC_OUT_BASE_ADDR_CR(0));
                break;
        case IPP_BUF_DEQUEUE:
-               gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));
-               gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));
-               gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));
+               gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(0));
+               gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(0));
+               gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(0));
                break;
        default:
                /* bypass */