compiler->has_dp2acc = dev_info->a6xx.has_dp2acc;
compiler->has_dp4acc = dev_info->a6xx.has_dp4acc;
- if (compiler->gen == 6) {
+ if (compiler->gen == 6 && options->shared_push_consts) {
compiler->shared_consts_base_offset = 504;
compiler->shared_consts_size = 8;
compiler->geom_shared_consts_size_quirk = 16;
/* If base_vertex should be lowered in nir */
bool lower_base_vertex;
+
+ bool shared_push_consts;
};
struct ir3_compiler {
.disable_cache = true,
.bindless_fb_read_descriptor = -1,
.bindless_fb_read_slot = -1,
- .storage_16bit = physical_device->info->a6xx.storage_16bit
+ .storage_16bit = physical_device->info->a6xx.storage_16bit,
+ .shared_push_consts = !TU_DEBUG(PUSH_CONSTS_PER_STAGE),
};
device->compiler =
ir3_compiler_create(NULL, &physical_device->dev_id, &ir3_options);
if (!layout->push_constant_size)
return IR3_PUSH_CONSTS_NONE;
+ if (TU_DEBUG(PUSH_CONSTS_PER_STAGE))
+ return IR3_PUSH_CONSTS_PER_STAGE;
+
if (tu6_shared_constants_enable(layout, compiler)) {
return IR3_PUSH_CONSTS_SHARED;
} else {
{ "perfc", TU_DEBUG_PERFC },
{ "flushall", TU_DEBUG_FLUSHALL },
{ "syncdraw", TU_DEBUG_SYNCDRAW },
+ { "push_consts_per_stage", TU_DEBUG_PUSH_CONSTS_PER_STAGE },
{ "rast_order", TU_DEBUG_RAST_ORDER },
{ "unaligned_store", TU_DEBUG_UNALIGNED_STORE },
{ "log_skip_gmem_ops", TU_DEBUG_LOG_SKIP_GMEM_OPS },
TU_DEBUG_PERFC = 1 << 9,
TU_DEBUG_FLUSHALL = 1 << 10,
TU_DEBUG_SYNCDRAW = 1 << 11,
- /* bit 12 is available */
+ TU_DEBUG_PUSH_CONSTS_PER_STAGE = 1 << 12,
TU_DEBUG_GMEM = 1 << 13,
TU_DEBUG_RAST_ORDER = 1 << 14,
TU_DEBUG_UNALIGNED_STORE = 1 << 15,