This reverts the radv_adjust_tile_swizzle change to unify the code.
Fixes:
529eb739fc4 - radeonsi/gfx11: add CB deltas
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
surf->tile_swizzle = xout.pipeBankXor;
+
+ /* Gfx11 should shift it by 10 bits instead of 8, and drivers already shift it by 8 bits,
+ * so shift it by 2 bits here.
+ */
+ if (info->gfx_level >= GFX11)
+ surf->tile_swizzle <<= 2;
}
bool use_dcc = false;
* - CMASK if it's TC-compatible or if the gen is GFX9
* - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
*/
- uint8_t tile_swizzle;
+ uint16_t tile_swizzle; /* it has 16 bits because gfx11 shifts it by 2 bits */
uint8_t fmask_tile_swizzle;
/* Use (1 << log2) to compute the alignment. */
tile_swizzle = iview->nbc_view.tile_swizzle;
}
- tile_swizzle = radv_adjust_tile_swizzle(device->physical_device, tile_swizzle);
-
cb->cb_color_base = va >> 8;
if (device->physical_device->rad_info.gfx_level >= GFX9) {
} else
va += (uint64_t)base_level_info->offset_256B * 256;
- swizzle = radv_adjust_tile_swizzle(device->physical_device, swizzle);
-
state[0] = va >> 8;
if (gfx_level >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
state[0] |= swizzle;
(pdevice->rad_info.gfx_level == GFX11 && bitsize == 32);
}
-static inline unsigned
-radv_adjust_tile_swizzle(const struct radv_physical_device *dev, unsigned pipe_bank_xor)
-{
- return pipe_bank_xor << (dev->rad_info.gfx_level >= GFX11 ? 2 : 0);
-}
-
/* radv_perfcounter.c */
void radv_perfcounter_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders);
void radv_perfcounter_emit_spm_reset(struct radeon_cmdbuf *cs);
1u << 31);
radeon_emit(
cmd_buffer->cs,
- (uint32_t)tiled_address |
- (radv_adjust_tile_swizzle(device->physical_device, image->planes[0].surface.tile_swizzle)
- << 8));
+ (uint32_t)tiled_address | (image->planes[0].surface.tile_swizzle << 8));
radeon_emit(cmd_buffer->cs, (uint32_t)(tiled_address >> 32));
radeon_emit(cmd_buffer->cs, 0);
radeon_emit(cmd_buffer->cs, ((tiled_width - 1) << 16));