radv/llvm: reduce the ESGS itemsize by using NIR IO assigned locations

There is no longer gaps in the ESGS ring.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7022>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 395676f..e993fb6 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2677,8 +2677,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
                radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
                                          pipeline->layout,
                                          &keys[MESA_SHADER_FRAGMENT],
-                                         &infos[MESA_SHADER_FRAGMENT],
-                                         radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_FRAGMENT));
+                                         &infos[MESA_SHADER_FRAGMENT]);
 
                /* TODO: These are no longer used as keys we should refactor this */
                keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
@@ -2729,8 +2728,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
                for (int i = 0; i < 2; i++) {
                        radv_nir_shader_info_pass(combined_nir[i],
                                                  pipeline->layout, &key,
-                                                 &infos[MESA_SHADER_TESS_CTRL],
-                                                 radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_TESS_CTRL));
+                                                 &infos[MESA_SHADER_TESS_CTRL]);
                }
 
                keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
@@ -2753,8 +2751,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
                        radv_nir_shader_info_pass(combined_nir[i],
                                                  pipeline->layout,
                                                  &keys[pre_stage],
-                                                 &infos[MESA_SHADER_GEOMETRY],
-                                                 radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_GEOMETRY));
+                                                 &infos[MESA_SHADER_GEOMETRY]);
                }
 
                filled_stages |= (1 << pre_stage);
@@ -2779,8 +2776,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
 
                radv_nir_shader_info_init(&infos[i]);
                radv_nir_shader_info_pass(nir[i], pipeline->layout,
-                                         &keys[i], &infos[i],
-                                         radv_use_llvm_for_stage(pipeline->device, i));
+                                         &keys[i], &infos[i]);
        }
 
        for (int i = 0; i < MESA_SHADER_STAGES; i++) {
@@ -3047,8 +3043,7 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
 
                        radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
                                                  pipeline->layout, &key,
-                                                 &info,
-                                                 radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_GEOMETRY));
+                                                 &info);
                        info.wave_size = 64; /* Wave32 not supported. */
                        info.ballot_bit_size = 64;
 

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index c8f2578..817d6ce 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -2477,8 +2477,7 @@ struct radv_shader_variant_key;
 void radv_nir_shader_info_pass(const struct nir_shader *nir,
                               const struct radv_pipeline_layout *layout,
                               const struct radv_shader_variant_key *key,
-                              struct radv_shader_info *info,
-                              bool use_llvm);
+                              struct radv_shader_info *info);
 
 void radv_nir_shader_info_init(struct radv_shader_info *info);
 

diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index d616cf7..c0af7cb 100644 (file)
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -598,8 +598,7 @@ void
 radv_nir_shader_info_pass(const struct nir_shader *nir,
                          const struct radv_pipeline_layout *layout,
                          const struct radv_shader_variant_key *key,
-                         struct radv_shader_info *info,
-                         bool use_llvm)
+                         struct radv_shader_info *info)
 {
        struct nir_function *func =
                (struct nir_function *)exec_list_get_head_const(&nir->functions);
@@ -752,26 +751,10 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
            key->vs_common_out.as_es) {
                struct radv_es_output_info *es_info =
                        nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
-
-               if (use_llvm) {
-                       /* The outputs may contain gaps, use the highest output index + 1 */
-                       uint32_t max_output_written = 0;
-                       uint64_t output_mask = nir->info.outputs_written;
-
-                       while (output_mask) {
-                               const int i = u_bit_scan64(&output_mask);
-                               unsigned param_index = shader_io_get_unique_index(i);
-
-                               max_output_written = MAX2(param_index, max_output_written);
-                       }
-                       es_info->esgs_itemsize = (max_output_written + 1) * 16;
-               } else {
-                       /* The outputs don't contain gaps, se we can use the number of outputs */
-                       uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
-                               ? info->vs.num_linked_outputs
-                               : info->tes.num_linked_outputs;
-                       es_info->esgs_itemsize = num_outputs_written * 16;
-               }
+               uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
+                       ? info->vs.num_linked_outputs
+                       : info->tes.num_linked_outputs;
+               es_info->esgs_itemsize = num_outputs_written * 16;
        }
 
        info->float_controls_mode = nir->info.float_controls_execution_mode;