Try to delete implicit uses, and add undef flags to explicit ones.
# RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu
# RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF
# RESULT-NEXT: G_STORE %{{[0-9]+}}(s32), %ptr(p1) :: (store (s32), addrspace 1)
-# RESULT-NEXT: S_ENDPGM 0, implicit %add(s64), implicit %{{[0-9]+}}(<2 x s16>), implicit %{{[0-9]+}}(s64)
+# RESULT-NEXT: S_ENDPGM 0{{$}}
---
name: f
-# RUN: llvm-reduce -mtriple=riscv32 --test %python --test-arg %p/instr-reduce.py %s -o %t
+# RUN: llvm-reduce --delta-passes=instructions -mtriple=riscv32 --test %python --test-arg %p/instr-reduce.py %s -o %t
# RUN: cat %t | FileCheck --match-full-lines %s
# REQUIRES: riscv-registered-target
# REQUIRES: riscv-registered-target
-# RUN: llvm-reduce -simplify-mir -mtriple=riscv64-- --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce -simplify-mir --delta-passes=instructions -mtriple=riscv64-- --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --check-prefix=RESULT %s < %t
# CHECK-INTERESTINGNESS: ADDW
# REQUIRES: amdgpu-registered-target
-# RUN: llvm-reduce -simplify-mir -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce -simplify-mir --delta-passes=instruction-flags -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --check-prefix=RESULT %s < %t
# CHECK-INTERESTINGNESS: V_ADD_F32
--- /dev/null
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-uses -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: V_MUL_F32_e32 %vgpr0
+# CHECK-INTERESTINGNESS: V_MUL_F32_e32 {{.*}}%vgpr1, %vgpr0
+
+# CHECK-INTERESTINGNESS: SI_CALL {{.*}}$vgpr0
+# CHECK-INTERESTINGNESS: SI_CALL {{.*}}$vgpr3
+
+
+# RESULT: %mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, undef %vgpr1, implicit $mode, implicit $exec
+# RESULT: %mul1:vgpr_32 = V_MUL_F32_e32 undef %vgpr1, %vgpr0, implicit $mode, implicit $exec
+# RESULT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+# RESULT: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
+# RESULT: $sgpr30_sgpr31 = SI_CALL undef %call_target, @callee, csr_amdgpu, implicit $vgpr0
+# RESULT: $sgpr30_sgpr31 = SI_CALL undef %call_target, @callee, csr_amdgpu, implicit $vgpr3
+# RESULT: %impdef:vreg_64 = IMPLICIT_DEF
+# RESULT: GLOBAL_STORE_DWORD undef %ptr, undef %impdef.sub1, 0, 0, implicit $exec
+# RESULT: undef %impdef.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+# RESULT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+# RESULT: S_BARRIER
+# RESULT: S_ENDPGM 0
+
+--- |
+ define void @func() {
+ ret void
+ }
+
+ declare void @callee()
+...
+
+---
+name: func
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ S_WAITCNT 0
+ %vgpr0:vgpr_32 = COPY $vgpr0
+ %vgpr1:vgpr_32 = COPY $vgpr1
+ %mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, %vgpr1, implicit $mode, implicit $exec
+ %mul1:vgpr_32 = V_MUL_F32_e32 %vgpr1, %vgpr0, implicit $mode, implicit $exec
+ %call_target:sreg_64 = IMPLICIT_DEF
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+ $vgpr1 = V_MOV_B32_e32 1, implicit $exec
+ $sgpr30_sgpr31 = SI_CALL %call_target, @callee, csr_amdgpu, implicit $vgpr0, implicit $vgpr1
+ $vgpr2 = V_MOV_B32_e32 2, implicit $exec
+ $vgpr3 = V_MOV_B32_e32 3, implicit $exec
+ $sgpr30_sgpr31 = SI_CALL %call_target, @callee, csr_amdgpu, implicit $vgpr2, implicit $vgpr3
+ %impdef:vreg_64 = IMPLICIT_DEF
+ %ptr:vreg_64 = IMPLICIT_DEF
+ GLOBAL_STORE_DWORD %ptr, %impdef.sub1, 0, 0, implicit $exec
+ %impdef.sub0 = V_MOV_B32_e32 0, implicit $exec
+ $scc = IMPLICIT_DEF
+ S_CBRANCH_SCC1 %bb.1, implicit $scc
+
+ bb.1:
+ S_BARRIER
+ S_ENDPGM 0, implicit %mul0, implicit %mul1
+...
+
# REQUIRES: amdgpu-registered-target
-# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
# CHECK-INTERESTINGNESS: V_ADD_U32
# REQUIRES: amdgpu-registered-target
-# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
# CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec
# REQUIRES: amdgpu-registered-target
-# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
# CHECK-INTERESTINGNESS: S_NOP 0
deltas/ReduceInstructionFlagsMIR.cpp
deltas/ReduceIRReferences.cpp
deltas/ReduceVirtualRegisters.cpp
+ deltas/ReduceRegisterUses.cpp
llvm-reduce.cpp
DEPENDS
#include "deltas/ReduceOperands.h"
#include "deltas/ReduceOperandsSkip.h"
#include "deltas/ReduceOperandsToArgs.h"
+#include "deltas/ReduceRegisterUses.h"
#include "deltas/ReduceSpecialGlobals.h"
#include "deltas/ReduceVirtualRegisters.h"
#include "llvm/Support/CommandLine.h"
DELTA_PASS("ir-block-references", reduceIRBlockReferencesDeltaPass) \
DELTA_PASS("ir-function-references", reduceIRFunctionReferencesDeltaPass) \
DELTA_PASS("instruction-flags", reduceInstructionFlagsMIRDeltaPass) \
+ DELTA_PASS("register-uses", reduceRegisterUsesMIRDeltaPass) \
DELTA_PASS("register-hints", reduceVirtualRegisterHintsDeltaPass)
static void runAllDeltaPasses(TestRunner &Tester) {
--- /dev/null
+//===- ReduceRegisterUses.cpp - Specialized Delta Pass --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a function which calls the Generic Delta pass in order
+// to reduce uninteresting register uses from the MachineFunction.
+//
+//===----------------------------------------------------------------------===//
+
+#include "ReduceRegisterUses.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+using namespace llvm;
+
+static void removeUsesFromFunction(Oracle &O, MachineFunction &MF) {
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
+ int NumOperands = MI.getNumOperands();
+ int NumRequiredOps = MI.getNumExplicitOperands() +
+ MI.getDesc().getNumImplicitDefs() +
+ MI.getDesc().getNumImplicitUses();
+
+ for (int I = NumOperands - 1; I >= 0; --I) {
+ MachineOperand &MO = MI.getOperand(I);
+ if (!MO.isReg() || !MO.readsReg())
+ continue;
+
+ Register Reg = MO.getReg();
+ if (Reg.isPhysical() && MRI.isReserved(Reg))
+ continue;
+
+ if (O.shouldKeep())
+ continue;
+
+ // Remove implicit operands. If the register is part of the fixed
+ // operand list, set to undef.
+ if (I >= NumRequiredOps)
+ MI.removeOperand(I);
+ else
+ MO.setIsUndef();
+ }
+ }
+ }
+}
+
+static void removeUsesFromModule(Oracle &O, ReducerWorkItem &WorkItem) {
+ for (const Function &F : WorkItem.getModule()) {
+ if (auto *MF = WorkItem.MMI->getMachineFunction(F))
+ removeUsesFromFunction(O, *MF);
+ }
+}
+
+void llvm::reduceRegisterUsesMIRDeltaPass(TestRunner &Test) {
+ outs() << "*** Reducing register uses...\n";
+ runDeltaPass(Test, removeUsesFromModule);
+}
--- /dev/null
+//===- ReduceRegisterUses.h - Specialized Delta Pass -----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a function which calls the Generic Delta pass in order
+// to reduce uninteresting register uses from the MachineFunction.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TOOLS_LLVM_REDUCE_DELTAS_REDUCEREGISTERUSES_H
+#define LLVM_TOOLS_LLVM_REDUCE_DELTAS_REDUCEREGISTERUSES_H
+
+#include "Delta.h"
+
+namespace llvm {
+void reduceRegisterUsesMIRDeltaPass(TestRunner &Test);
+} // namespace llvm
+
+#endif