- description:
Freescale Vybrid Platform Device Tree Bindings
- For the Vybrid SoC familiy all variants with DDR controller are supported,
+ For the Vybrid SoC family all variants with DDR controller are supported,
which is the VF5xx and VF6xx series. Out of historical reasons, in most
- places the kernel uses vf610 to refer to the whole familiy.
+ places the kernel uses vf610 to refer to the whole family.
The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
core support.
items:
number of clocks:
- a set of core clocks
- - a set of gatable clocks
+ - a set of gateable clocks
Those clocks can be referenced by other Device Tree nodes using two
cells:
- The first cell must be 0 or 1. 0 for the core clocks and 1 for the
- gatable clocks.
- - The second cell identifies the particular core clock or gatable
+ gateable clocks.
+ - The second cell identifies the particular core clock or gateable
clocks.
The following clocks are available:
- 0 3 Core
- 0 4 NAND core
- 0 5 SDIO core
- - Gatable clocks
+ - Gateable clocks
- 1 0 Audio
- 1 1 Comm Unit
- 1 2 NAND
The mipi0a controller also uses the common power domain from
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
-The available power doamins are defined in dt-bindings/power/mt*-power.h.
+The available power domains are defined in dt-bindings/power/mt*-power.h.
Example:
The vcodecsys controller also uses the common power domain from
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
-The available power doamins are defined in dt-bindings/power/mt*-power.h.
+The available power domains are defined in dt-bindings/power/mt*-power.h.
Example:
- const: msi,primo81
- const: allwinner,sun6i-a31s
- - description: Emlid Neutis N5 Developper Board
+ - description: Emlid Neutis N5 Developer Board
items:
- const: emlid,neutis-n5-devboard
- const: emlid,neutis-n5
- const: allwinner,sun50i-h5
- - description: Emlid Neutis N5H3 Developper Board
+ - description: Emlid Neutis N5H3 Developer Board
items:
- const: emlid,neutis-n5h3-devboard
- const: emlid,neutis-n5h3
description: |
This document defines device tree properties common to most Parallel
ATA (PATA, also known as IDE) AT attachment storage devices.
- It doesn't constitue a device tree binding specification by itself but is
+ It doesn't constitute a device tree binding specification by itself but is
meant to be referenced by device tree bindings.
The PATA (IDE) controller-specific device tree bindings are responsible for
brcm,gisb-arb-master-names:
$ref: /schemas/types.yaml#/definitions/string-array
description: >
- String list of the litteral name of the GISB masters. Should match the
+ String list of the literal name of the GISB masters. Should match the
number of bits set in brcm,gisb-master-mask and the order in which they
appear from MSB to LSB.
title: NVIDIA Tegra ACONNECT Bus
description: |
- The Tegra ACONNECT bus is an AXI switch which is used to connnect various
+ The Tegra ACONNECT bus is an AXI switch which is used to connect various
components inside the Audio Processing Engine (APE). All CPU accesses to
the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All
- devices accessed via the ACONNNECT are described by child-nodes.
+ devices accessed via the ACONNECT are described by child-nodes.
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Allwinner A10 Gatable Oscillator Clock
+title: Allwinner A10 Gateable Oscillator Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>
Alphascale Clock Controller
-The ACC (Alphascale Clock Controller) is responsible of choising proper
-clock source, setting deviders and clock gates.
+The ACC (Alphascale Clock Controller) is responsible for choosing proper
+clock source, setting dividers and clock gates.
Required properties for the ACC node:
- compatible: must be "alphascale,asm9260-clock-controller"
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
- clocks : parent clock phandle
-- reg - pll control0 and pll multipler registers
+- reg - pll control0 and pll multiplier registers
- reg-names : control, multiplier and post-divider. The multiplier and
post-divider registers are applicable only for main pll clock
- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
"base_ssp0_clk", "base_sdio_clk";
};
- /* A user of CCU brach clocks */
+ /* A user of CCU branch clocks */
uart1: serial@40082000 {
...
clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
32 kHz oscillator driver with power up/down and clock gating. Next
is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
-These clocks are used by the RTC and the Event Router peripherials.
-The 32 kHz can also be routed to other peripherials to enable low
+These clocks are used by the RTC and the Event Router peripherals.
+The 32 kHz can also be routed to other peripherals to enable low
power modes.
This binding uses the common clock binding:
Required properties:
- compatible: "maxim,max9485"
-- clocks: Input clock, must provice 27.000 MHz
+- clocks: Input clock, must provide 27.000 MHz
- clock-names: Must be set to "xclk"
- #clock-cells: From common clock binding; shall be set to 1
- description: Sleep clock source
- description: PCIE 0 Pipe clock source (Optional clock)
- description: PCIE 1 Pipe clock source (Optional clock)
- - description: PCIE 1 Phy Auxillary clock source (Optional clock)
+ - description: PCIE 1 Phy Auxiliary clock source (Optional clock)
- description: UFS Phy Rx symbol 0 clock source (Optional clock)
- description: UFS Phy Rx symbol 1 clock source (Optional clock)
- description: UFS Phy Tx symbol 0 clock source (Optional clock)
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region. ACC v1 is currently used as a
- clock-controller for enabling the cpu and hanling the aux clocks.
+ clock-controller for enabling the cpu and handling the aux clocks.
properties:
compatible:
else:
description: |
Other SC9863a clock nodes should be the child of a syscon node in
- which compatible string shoule be:
+ which compatible string should be:
"sprd,sc9863a-glbregs", "syscon", "simple-mfd"
The 'reg' property for the clock node is also required if there is a sub
gate or adjust the parent rate via a divider or multiplier.
By default the "clocks" property lists the parents in the same order
-as they are programmed into the regster. E.g:
+as they are programmed into the register. E.g:
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
- clocks: list of clock identifiers which are external input clocks to the
given clock controller. Please refer the next section to find
the input clocks for a given controller.
-- clock-names: list of names of clocks which are exteral input clocks to the
+- clock-names: list of names of clocks which are external input clocks to the
given clock controller.
Input clocks for top clock controller:
state as defined in 7.4.2 Sink Electrical Parameters of USB Power Delivery Specification
Revision 3.0, Version 1.2. When the property is set, the port requests pSnkStby(2.5W -
5V@500mA) upon entering SNK_DISCOVERY(instead of 3A or the 1.5A, Rp current advertised, during
- SNK_DISCOVERY) and the actual currrent limit after reception of PS_Ready for PD link or during
+ SNK_DISCOVERY) and the actual current limit after reception of PS_Ready for PD link or during
SNK_READY for non-pd link.
type: boolean
each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
Exynos PPMU driver uses the devfreq-event class to provide event data to
various devfreq devices. The devfreq devices would use the event data when
- derterming the current state of each IP.
+ determining the current state of each IP.
properties:
compatible:
Required children nodes:
Children nodes are encoding available output ports and their connections
- to external devices using the OF graph reprensentation (see ../graph.txt).
+ to external devices using the OF graph representation (see ../graph.txt).
At least one port node is required.
Optional properties in grandchild nodes:
description: |
This document defines device tree properties for the Synopsys DesignWare MIPI
- DSI host controller. It doesn't constitue a device tree binding specification
+ DSI host controller. It doesn't constitute a device tree binding specification
by itself but is meant to be referenced by platform-specific device tree
bindings.
-* Currus Logic CLPS711X Framebuffer
+* Cirrus Logic CLPS711X Framebuffer
Required properties:
- compatible: Shall contain "cirrus,ep7209-fb".
- Rob Clark <robdclark@gmail.com>
description:
- This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
+ This is the bindings documentation for the Mobile Display Subsystem(MDSS) that
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
properties:
The panel itself contains:
- AT24C16C EEPROM holding panel identification and timing requirements
- AR1021 resistive touch screen controller (optional)
- - FT5x6 capacitive touch screnn controller (optional)
+ - FT5x6 capacitive touch screen controller (optional)
- GT911/GT928 capacitive touch screen controller (optional)
The above chips share same I2C bus. The EEPROM is factory preprogrammed with
description: |
This document defines device tree properties common to several classes of
- display panels. It doesn't constitue a device tree binding specification by
+ display panels. It doesn't constitute a device tree binding specification by
itself but is meant to be referenced by device tree bindings.
When referenced from panel device tree bindings the properties defined in this
# optional when driving an eDP output
nvidia,dpaux:
- description: phandle to a DispayPort AUX interface
+ description: phandle to a DisplayPort AUX interface
$ref: /schemas/types.yaml#/definitions/phandle
allOf:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
Bitmask of channels to reserve for devices that need a specific
- channel. These channels will only be assigned when explicitely
+ channel. These channels will only be assigned when explicitly
requested by a client. The primary use for this is channels 0 and
1, which can be configured to have special behaviour for NAND/BCH
when using programmable firmware.
Required properties:
- compatible: Should be "nvidia,<chip>-apbdma"
-- reg: Should contain DMA registers location and length. This shuld include
+- reg: Should contain DMA registers location and length. This should include
all of the per-channel registers.
- interrupts: Should contain all of the per-channel DMA interrupts.
- clocks: Must contain one entry, for the module clock.
qcom,controlled-remotely:
type: boolean
description:
- Indicates that the bam is controlled by remote proccessor i.e. execution
+ Indicates that the bam is controlled by remote processor i.e. execution
environment.
qcom,ee:
memcpy-channels:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: Array of u32 elements indicating which channels on the DMA
- engine are elegible for memcpy transfers
+ engine are eligible for memcpy transfers
required:
- "#dma-cells"
will be disabled.
* During Partial Reconfiguration of a specific region, that region's bridge
will be used to gate the busses. Traffic to other regions is not affected.
- * In some implementations, the FPGA Manager transparantly handles gating the
+ * In some implementations, the FPGA Manager transparently handles gating the
buses, eliminating the need to show the hardware FPGA bridges in the
device tree.
* An FPGA image may create a set of reprogrammable regions, each having its
constraints required to make partial reconfiguration work[1] [2] [3], but a few
deserve quick mention.
-A persona must have boundary connections that line up with those of the partion
+A persona must have boundary connections that line up with those of the partition
or region it is designed to go into.
During programming, transactions through those connections must be stopped and
- gpio-controller: Marks the device node as a GPIO controller.
- interrupts: The EXT_INT_0 parent interrupt resource must be listed first.
- interrupt-cells: Should be two.
- - first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N.
+ - first cell is 0-N corresponding for EXT_INT_0 to EXT_INT_N.
- second cell is used to specify flags.
- interrupt-controller: Marks the device node as an interrupt controller.
- apm,nr-gpios: Optional, specify number of gpios pin.
description: |
Synopsys DesignWare GPIO controllers have a configurable number of ports,
each of which are intended to be represented as child nodes with the generic
- GPIO-controller properties as desribed in this bindings file.
+ GPIO-controller properties as described in this bindings file.
maintainers:
- Hoan Tran <hoan@os.amperecomputing.com>
deprecated: true
description:
Name of the hwmod associated with the GPIO. Needed on some legacy OMAP
- SoCs which have not been converted to the ti,sysc interconnect hierarachy.
+ SoCs which have not been converted to the ti,sysc interconnect hierarchy.
ti,no-reset-on-init:
$ref: /schemas/types.yaml#/definitions/flag
deprecated: true
description:
Do not reset on init. Used with ti,hwmods on some legacy OMAP SoCs which
- have not been converted to the ti,sysc interconnect hierarachy.
+ have not been converted to the ti,sysc interconnect hierarchy.
patternProperties:
"^(.+-hog(-[0-9]+)?)$":
shunt-resistor-micro-ohms:
description:
- The value of curent sense resistor in microohms. If not provided,
+ The value of current sense resistor in microohms. If not provided,
the current reading and overcurrent alert is disabled.
adi,shutdown-threshold-microamp:
- Nuno Sá <nuno.sa@analog.com>
description: |+
- Bindings for the Analog Devices AXI FAN Control driver. Spefications of the
+ Bindings for the Analog Devices AXI FAN Control driver. Specifications of the
core can be found in:
https://wiki.analog.com/resources/fpga/docs/axi_fan_control
shunt-resistor-micro-ohms:
description:
- The value of curent sense resistor in microohms.
+ The value of current sense resistor in microohms.
required:
- compatible
- aspeed,fan-tach-ch : should specify the Fan tach input channel.
integer value in the range 0 through 15, with 0 indicating
Fan tach channel 0 and 15 indicating Fan tach channel 15.
- Atleast one Fan tach input channel is required.
+ At least one Fan tach input channel is required.
Examples:
in7. Otherwise the pin is set as FAN2 input.
- vcc-supply: a Phandle for the regulator supplying power, can be
- cofigured to measure 5.0V power supply. Default is 3.3V.
+ configured to measure 5.0V power supply. Default is 3.3V.
Example:
-Lantiq cpu temperatur sensor
+Lantiq cpu temperature sensor
Requires node properties:
- compatible value :
reg:
items:
- description: PVT common registers
- - description: PVT temprature sensor registers
+ - description: PVT temperature sensor registers
- description: PVT process detector registers
- description: PVT voltage monitor registers
fan subnode format:
===================
Under fan subnode can be upto 8 child nodes, each child node representing a fan.
-Each fan subnode must have one PWM channel and atleast one Fan tach channel.
+Each fan subnode must have one PWM channel and at least one Fan tach channel.
For PWM channel can be configured cooling-levels to create cooling device.
Cooling device could be bound to a thermal zone for the thermal control.
The SHTC1, SHTW1 and SHTC3 are digital humidity and temperature sensors
designed especially for battery-driven high-volume consumer electronics
applications.
- For further information refere to Documentation/hwmon/shtc1.rst
+ For further information refer to Documentation/hwmon/shtc1.rst
This binding document describes the binding for the hardware monitor
portion of the driver.
shunt-resistor-micro-ohms:
description: |
- If 0, the calibration process will be skiped and the current and power
+ If 0, the calibration process will be skipped and the current and power
measurement engine will not work. Temperature and voltage measurement
will continue to work. The shunt value also need to respect:
rshunt <= pga-gain * 40 * 1000 * 1000.
maxItems: 1
shunt-resistor-micro-ohms:
- description: The value of curent sense resistor in microohms.
+ description: The value of current sense resistor in microohms.
default: 255000
minimum: 250000
maximum: 255000
"source" for I2C source (parent) clock,
"enable" for I2C module enable clock.
- clocks: Should contain a clock specifier for each entry in clock-names.
-- clock-frequency: Constains desired I2C bus clock frequency in Hz.
+- clock-frequency: Contains desired I2C bus clock frequency in Hz.
- #address-cells: Should be 1 to describe address cells for I2C device address.
- #size-cells: Should be 0 means no size cell for I2C device address.
|27 |FPD Internal voltage measurement, VCC_PSINTFP (supply5). |Voltage
|28 |PS Auxiliary voltage measurement (supply6). |Voltage
|29 |PL VCCADC voltage measurement (vccams). |Voltage
- |30 |Differential analog input signal voltage measurment. |Voltage
+ |30 |Differential analog input signal voltage measurement. |Voltage
|31 |VUser0 voltage measurement (supply7). |Voltage
|32 |VUser1 voltage measurement (supply8). |Voltage
|33 |VUser2 voltage measurement (supply9). |Voltage
$id: http://devicetree.org/schemas/iio/cdc/adi,ad7150.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Analog device AD7150 and similar capacitance to digital convertors.
+title: Analog device AD7150 and similar capacitance to digital converters.
maintainers:
- Jonathan Cameron <jic23@kernel.org>
description: |
This document defines device tree properties common to several iio
- sensors. It doesn't constitue a device tree binding specification by itself but
+ sensors. It doesn't constitute a device tree binding specification by itself but
is meant to be referenced by device tree bindings.
When referenced from sensor tree bindings the properties defined in this
items:
- const: lo_in
description:
- External clock that provides the Local Oscilator input.
+ External clock that provides the Local Oscillator input.
vcm-supply:
description:
- Eugene Zaikonnikov <ez@norophonic.com>
description: |
- Relative humidity and tempereature sensors on I2C bus
+ Relative humidity and temperature sensors on I2C bus
Datasheets are available at:
http://www.ti.com/product/HDC2010/datasheet
reset-gpios:
description:
Optional GPIO for resetting the device.
- If not present the device is not resetted during the probe.
+ If not present the device is not reset during the probe.
maxItems: 1
honeywell,pmin-pascal:
- Matt Ranostay <matt.ranostay@konsulko.com>
description:
- This lightening distance sensor uses an I2C or SPI interface. The
+ This lightning distance sensor uses an I2C or SPI interface. The
binding currently only covers the SPI option.
properties:
interrupts:
description: interrupt line(s) connected to the DRDY line(s) and/or the
- Intertial interrupt lines INT1 and INT2 if these exist. This means up to
+ Inertial interrupt lines INT1 and INT2 if these exist. This means up to
three interrupts, and the DRDY must be the first one if it exists on
the package. The trigger edge of the interrupts is sometimes software
configurable in the hardware so the operating system should parse this
mode.
- syna,sensor-type: Set the sensor type. 1 for touchscreen 2 for touchpad.
- syna,disable-report-mask: Mask for disabling posiiton reporting. Used to
- disable reporing absolute position data.
-- syna,rezero-wait-ms: Time in miliseconds to wait after issuing a rezero
+ disable reporting absolute position data.
+- syna,rezero-wait-ms: Time in milliseconds to wait after issuing a rezero
command.
- ti,x-plate-ohms: X-plate resistance in ohms.
Optional properties:
-- gpios: the interrupt gpio the chip is connected to (trough the penirq pin).
+- gpios: the interrupt gpio the chip is connected to (through the penirq pin).
The penirq pin goes to low when the panel is touched.
(see GPIO binding[1] for more details).
- interrupts: (gpio) interrupt to which the chip is connected
The 2nd cell contains the interrupt number for the interrupt type.
SPI interrupts are in the range [0-987]. PPI interrupts are in the
- range [0-15]. Extented SPI interrupts are in the range [0-1023].
+ range [0-15]. Extended SPI interrupts are in the range [0-1023].
Extended PPI interrupts are in the range [0-127].
The 3rd cell is the flags, encoded as follows:
25: DMA9
26: DMA10
27: DMA11-14 - shared interrupt for DMA 11 to 14
-28: DMAALL - triggers on all dma interrupts (including chanel 15)
+28: DMAALL - triggers on all dma interrupts (including channel 15)
29: AUX
30: ARM
31: VPUDMA
..
31 ........................ X
- The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
+ The BCM3380 Level 1 / Level 2 interrupt controller shows up in various forms
on many BCM338x/BCM63xx chipsets. It has the following properties:
- outputs a single interrupt signal to its interrupt controller parent
mediatek,bled-ocp-shutdown:
description: |
- Enable the backlight shutdown when OCP level triggerred.
+ Enable the backlight shutdown when OCP level triggered.
type: boolean
mediatek,bled-ocp-microamp:
max-cur:
$ref: /schemas/types.yaml#/definitions/uint8
- description: Maximun current at each LED channel.
+ description: Maximum current at each LED channel.
reg:
maximum: 8
max-cur:
$ref: /schemas/types.yaml#/definitions/uint8
- description: Maximun current at each LED channel.
+ description: Maximum current at each LED channel.
reg:
description: |
description: >
A list of integer pairs, where each pair represent the dtest line the
particular channel should be connected to and the flags denoting how the
- value should be outputed, as defined in the datasheet. The number of
+ value should be outputted, as defined in the datasheet. The number of
pairs should be the same as the number of channels.
items:
items:
where N is the value specified by 2nd cell above. If FlexRM
does not get required number of completion messages in time
specified by this cell then it will inject one MSI interrupt
- to CPU provided atleast one completion message is available.
+ to CPU provided at least one completion message is available.
Optional properties:
--------------------
a corresponding sysc interconnect node.
This property is only needed on some legacy OMAP SoCs which have not
- yet been converted to the ti,sysc interconnect hierarachy, but is
+ yet been converted to the ti,sysc interconnect hierarchy, but is
otherwise considered obsolete.
patternProperties:
description: |-
The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
stream. The direction can be either parallel-in -> csi-out or csi-in ->
- parallel-out The chip is programmable trough I2C and SPI but the SPI
+ parallel-out The chip is programmable through I2C and SPI but the SPI
interface is only supported in parallel-in -> csi-out mode.
Note that the current device tree bindings only support the
==============================
- sdtv-standards: Set the possible signals to which the hardware tries to lock
- instead of using the autodetection mechnism. Please look at
+ instead of using the autodetection mechanism. Please look at
[1] for more information.
[1] Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml.
controls the information of each hardware independent which include clk/power/irq.
There are two workqueues in parent device: lat workqueue and core workqueue. They are used
- to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
+ to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer,
then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
writing the result to output buffer, disable hardware when core decode done. These two
minimum: 0
maximum: 31
description: the hardware id of this larb. It's only required when this
- hardward id is not consecutive from its M4U point of view.
+ hardware id is not consecutive from its M4U point of view.
required:
- compatible
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the phy side CA line
- (incluing command line, address line and clock line) drive strength.
+ (including command line, address line and clock line) drive strength.
default: 40
rockchip,phy_ddr3_dq_drv:
description:
Defines the self-refresh power down idle period in which memories are
placed into self-refresh power down mode if bus is idle for
- srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.
+ srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only.
rockchip,standby-idle-ns:
description:
description:
The Zynq DDR ECC controller has an optional ECC support in half-bus width
- (16-bit) configuration. It is cappable of correcting single bit ECC errors
+ (16-bit) configuration. It is capable of correcting single bit ECC errors
and detecting double bit ECC errors.
properties:
as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
management and bus snoop configuration.
- * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
+ * A set of SuperIO[3] scratch registers enabling implementation of e.g. custom
hardware management protocols for handover between the host and baseboard
management controller.
BD9576 and BD9573 VOUT1 regulator enable state can be individually
controlled by a GPIO. This is dictated by state of vout1-en pin during
the PMIC startup. If vout1-en is LOW during PMIC startup then the VOUT1
- enable sate is controlled via this pin. Set this property if vout1-en
+ enable state is controlled via this pin. Set this property if vout1-en
is wired to be down at PMIC start-up.
type: boolean
rohm,hw-timeout-ms:
maxItems: 2
description:
- Watchog timeout in milliseconds. If single value is given it is
+ Watchdog timeout in milliseconds. If single value is given it is
the maximum timeout. Eg. if pinging watchdog is not done within this time
limit the watchdog will be triggered. If two values are given watchdog
is configured in "window mode". Then first value is limit for short-ping
- const: audioclk
stericsson,earpeice-cmv:
- description: Earpeice voltage
+ description: Earpiece voltage
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 950, 1100, 1270, 1580 ]
with power.
ab8500_ldo_aux1:
- description: The voltage for the auxilary LDO regulator 1
+ description: The voltage for the auxiliary LDO regulator 1
type: object
$ref: ../regulator/regulator.yaml#
unevaluatedProperties: false
ab8500_ldo_aux2:
- description: The voltage for the auxilary LDO regulator 2
+ description: The voltage for the auxiliary LDO regulator 2
type: object
$ref: ../regulator/regulator.yaml#
unevaluatedProperties: false
ab8500_ldo_aux3:
- description: The voltage for the auxilary LDO regulator 3
+ description: The voltage for the auxiliary LDO regulator 3
type: object
$ref: ../regulator/regulator.yaml#
unevaluatedProperties: false
ab8500_ldo_aux4:
- description: The voltage for the auxilary LDO regulator 4
+ description: The voltage for the auxiliary LDO regulator 4
only present on AB8505
type: object
$ref: ../regulator/regulator.yaml#
unevaluatedProperties: false
ab8500_ldo_aux5:
- description: The voltage for the auxilary LDO regulator 5
+ description: The voltage for the auxiliary LDO regulator 5
only present on AB8505
type: object
$ref: ../regulator/regulator.yaml#
unevaluatedProperties: false
ab8500_ldo_aux6:
- description: The voltage for the auxilary LDO regulator 6
+ description: The voltage for the auxiliary LDO regulator 6
only present on AB8505
type: object
$ref: ../regulator/regulator.yaml#
# There is never any AUX7 regulator which is confusing
ab8500_ldo_aux8:
- description: The voltage for the auxilary LDO regulator 8
+ description: The voltage for the auxiliary LDO regulator 8
only present on AB8505
type: object
$ref: ../regulator/regulator.yaml#
$ref: ../regulator/regulator.yaml#
db8500_vrf1:
- description: RF transciever voltage regulator.
+ description: RF transceiver voltage regulator.
type: object
$ref: ../regulator/regulator.yaml#
Optional properties:
- marvell,detect-delay-ms: sets the detection delay timeout in ms.
-In addition to the properties described in this docuent, the details
+In addition to the properties described in this document, the details
described in mmc.txt are supported.
Examples:
| card | -- CIRQ --> | hsmmc | -- IRQ --> | CPU |
------ ------- -----
-In suspend the fclk is off and the module is disfunctional. Even register reads
+In suspend the fclk is off and the module is dysfunctional. Even register reads
will fail. A small logic in the host will request fclk restore, when an
external event is detected. Once the clock is restored, the host detects the
event normally. Since am33xx doesn't have this line it never wakes from
-* Broadcom Starfighter 2 integrated swich
+* Broadcom Starfighter 2 integrated switch
See dsa/brcm,bcm7445-switch-v4.0.yaml for the documentation.
will be disabled.
- bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
- a resonable value will be calculated.
+ a reasonable value will be calculated.
- bosch,disconnect-rx0-input : see data sheet.
$id: http://devicetree.org/schemas/net/dsa/brcm,sf2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Broadcom Starfighter 2 integrated swich
+title: Broadcom Starfighter 2 integrated switch
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
$ref: /schemas/types.yaml#/definitions/flag
description:
If set, indicates that PHY will disable swap of the
- TX/RX lanes. This property allows the PHY to work correcly after
+ TX/RX lanes. This property allows the PHY to work correctly after
e.g. wrong bootstrap configuration caused by issues in PCB
layout design.
type: boolean
description:
If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
- Otherwise, PHY WOL is perferred.
+ Otherwise, PHY WOL is preferred.
required:
- compatible
- usb424,9906 # SMSC9505A USB Ethernet Device (HAL)
- usb424,9907 # SMSC9500 USB Ethernet Device (Alternate ID)
- usb424,9908 # SMSC9500A USB Ethernet Device (Alternate ID)
- - usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Devic. ID)
+ - usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Device ID)
- usb424,9e00 # SMSC9500A USB Ethernet Device
- usb424,9e01 # SMSC9505A USB Ethernet Device
- usb424,9e08 # SMSC LAN89530 USB Ethernet Device
type: boolean
description: |
For I2C type of connection. Specifies that the chip read event shall be
- trigged on falling edge.
+ triggered on falling edge.
i2c-int-rising:
type: boolean
description: |
For I2C type of connection. Specifies that the chip read event shall be
- trigged on rising edge.
+ triggered on rising edge.
break-control:
type: boolean
- reg: Address and length of the register set for the device
- interrupts: Should contain the SXGBE interrupts
These interrupts are ordered by fixed and follows variable
- trasmit DMA interrupts, receive DMA interrupts and lpi interrupt.
+ transmit DMA interrupts, receive DMA interrupts and lpi interrupt.
index 0 - this is fixed common interrupt of SXGBE and it is always
available.
- index 1 to 25 - 8 variable trasmit interrupts, variable 16 receive interrupts
+ index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
and 1 optional lpi interrupt.
- phy-mode: String, operation mode of the PHY interface.
Supported values are: "sgmii", "xgmii".
It depends on the SoC configuration.
- snps,read-requests: Number of read requests that the AXI port can issue.
It depends on the SoC configuration.
-- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
+- snps,burst-map: Bitmap of allowed AXI burst lengths, with the LSB
representing 4, then 8 etc.
- snps,txpbl: DMA Programmable burst length for the TX DMA
- snps,rxpbl: DMA Programmable burst length for the RX DMA
MAC can generate it.
- st,tx-retime-src: This specifies which clk is wired up to the mac for
retimeing tx lines. This is totally board dependent and can take one of the
- posssible values from "txclk", "clk_125" or "clkgen".
+ possible values from "txclk", "clk_125" or "clkgen".
If not passed, the internal clock will be used by default.
- sti-ethclk: this is the phy clock.
- sti-clkconf: this is an extra sysconfig register, available in new SoCs,
This core can be used in all three modes of operation(10/100/1000 Mb/s).
The Management Data Input/Output (MDIO) interface is used to configure the
Speed of operation. This core can switch dynamically between the three
-Different speed modes by configuring the conveter register through mdio write.
+Different speed modes by configuring the converter register through mdio write.
This converter sits between the ethernet MAC and the external phy.
MAC <==> GMII2RGMII <==> RGMII_PHY
- altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
- altr,tlb-num-entries: Specifies the number of entries in the TLB.
- altr,tlb-ptr-sz: Specifies size of TLB pointer.
-- altr,has-mul: Specifies CPU hardware multipy support, should be 1.
+- altr,has-mul: Specifies CPU hardware multiply support, should be 1.
- altr,has-mmu: Specifies CPU support MMU support, should be 1.
- altr,has-initda: Specifies CPU support initda instruction, should be 1.
- altr,reset-addr: Specifies CPU reset address
infrastructure shall provide a non-volatile memory with a table whose the
content is well specified and gives many information about the manufacturer
(name, country of manufacture, etc) as well as device caracteristics (serial
- number, hardware version, mac addresses, etc). The underlaying device type
+ number, hardware version, mac addresses, etc). The underlying device type
(flash, EEPROM,...) is not specified. The exact location of each value is also
dynamic and should be discovered at run time because it depends on the
parameters the manufacturer decided to embed.
- #size-cells: Must be 0.
The INNO USB2 PHY device should be a child node of peripheral controller that
-contains the PHY configuration register, and each device suppports up to 2 PHY
+contains the PHY configuration register, and each device supports up to 2 PHY
ports which are represented as child nodes of INNO USB2 PHY device.
Required properties for PHY port node:
- clocks: Must contain an entry for each entry in clock-names.
See ../clock/clock-bindings.txt for details.
- clock-names: Must include "usb_phy".
- - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
+ - img,cr-top: Must contain a phandle to the CR_TOP syscon node.
- img,refclk: Indicates the reference clock source for the USB PHY.
See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
- compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy"
- reg: base address and length of the registers
- clocks - A single clock. From common clock binding.
-- #phys-cells: should be 0. From commmon phy binding.
+- #phys-cells: should be 0. From common phy binding.
- resets: reference to the reset controller
Example:
- Heiko Stuebner <heiko@sntech.de>
description: |
- The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich
+ The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
properties:
description:
GPIO to signal Type-C cable orientation for lane swap.
If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
- achieve the funtionality of an external type-C plug flip mux.
+ achieve the functionality of an external type-C plug flip mux.
typec-dir-debounce-ms:
minimum: 100
- ctrl-module : phandle of the control module used by PHY driver to power on
the PHY.
-Recommended properies:
+Recommended properties:
- syscon-phy-power : phandle/offset pair. Phandle to the system control
module and the register offset to power on/off the PHY.
# It's pretty scary, but the basic idea is that:
# - One node name can start with either s- or r- for PRCM nodes,
# - Then, the name itself can be any repetition of <string>- (to
- # accomodate with nodes like uart4-rts-cts-pins), where each
+ # accommodate with nodes like uart4-rts-cts-pins), where each
# string can be either starting with 'p' but in a string longer
# than 3, or something that doesn't start with 'p',
# - Then, the bank name is optional and will be between pa and pg,
description:
The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA)
- controller allows assiging any of 256 possible functions to any of
+ controller allows assigning any of 256 possible functions to any of
48 IO pins of the SoC. Pin function configuration is performed on
a per-pin basis.
mediatek,pull-up-adv:
description: |
- Pull up setings for 2 pull resistors, R0 and R1. User can
+ Pull up settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as
below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
mediatek,pull-up-adv:
description: |
- Pull up setings for 2 pull resistors, R0 and R1. User can
+ Pull up settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as
below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
mediatek,pull-up-adv:
description: |
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
- Pull up setings for 2 pull resistors, R0 and R1. Valid arguments
+ Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
mediatek,pull-down-adv:
description: |
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
- Pull down setings for 2 pull resistors, R0 and R1. Valid arguments
+ Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
mediatek,pull-up-adv:
description: |
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
- Pull up setings for 2 pull resistors, R0 and R1. Valid arguments
+ Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
mediatek,pull-down-adv:
description: |
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
- Pull down setings for 2 pull resistors, R0 and R1. Valid arguments
+ Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
mediatek,pull-up-adv:
description: |
- Pull up setings for 2 pull resistors, R0 and R1. User can
+ Pull up settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as
below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
deprecated: true
description: |
DEPRECATED: Please use bias-pull-up instead.
- Pull up setings for 2 pull resistors, R0 and R1. User can
+ Pull up settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as
below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,
reference-out
-Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These
+There are also customised properties for the GPIO1, GPIO2 and GPIO3. These
customised properties are required to configure FPS configuration parameters
of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more
detail of Flexible Power Sequence (FPS).
Valid values for function properties are: gpio.
-Theres is also not customised properties for any GPIO.
+There are also not customised properties for any GPIO.
Example:
--------
pad driving level, system control select and so on ("domain pad
driving level": One pin can output 3.0v or 1.8v, depending on the
related domain pad driving selection, if the related domain pad
-slect 3.0v, then the pin can output 3.0v. "system control" is used
+select 3.0v, then the pin can output 3.0v. "system control" is used
to choose one function (like: UART0) for which system, since we
have several systems (AP/CP/CM4) on one SoC.).
- compatible = "pmem-region"
- reg = <base, size>;
- The reg property should specificy an address range that is
+ The reg property should specify an address range that is
translatable to a system physical address range. This address
range should be mappable as normal system memory would be
(i.e cacheable).
node implies no special relationship between the two ranges.
Optional properties:
- - Any relevant NUMA assocativity properties for the target platform.
+ - Any relevant NUMA associativity properties for the target platform.
- volatile; This property indicates that this region is actually
backed by non-persistent memory. This lets the OS know that it
pd-node:
type: object
description:
- PM domain node representing a PM domain. This node hould be named by
+ PM domain node representing a PM domain. This node should be named by
the real power area name, and thus its name should be unique.
properties:
$id: http://devicetree.org/schemas/power/supply/sbs,sbs-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: SBS compliant manger
+title: SBS compliant manager
maintainers:
- Sebastian Reichel <sre@kernel.org>
Snoop ID Port Mapping registers, which are part of the CoreNet
Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from
- these registers should be set if the coresponding CPU should be
+ these registers should be set if the corresponding CPU should be
snooped. This property defines a bitmask which selects the bit
that should be set if this cpu should be snooped.
with distinct functionality.
The first register range describes the CoreNet Debug Controller
- functionalty to perform transaction and transaction attribute matches.
+ functionality to perform transaction and transaction attribute matches.
The second register range describes the CoreNet Debug Controller
- functionalty to trigger event notifications and debug traces.
+ functionality to trigger event notifications and debug traces.
EXAMPLE
dcsr-corenet {
- fsl,liodn: Specifies the LIODN to be used for Job Ring. This
property is normally set by firmware. Value
is of 12-bits which is the LIODN number for this JR.
- This property is used by the IOMMU (PAMU) to distinquish
+ This property is used by the IOMMU (PAMU) to distinguish
transactions from this JR and than be able to do address
translation & protection accordingly.
- compatible : should be "nintendo,flipper-pic"
-1.c) The Digital Signal Procesor (DSP) node
+1.c) The Digital Signal Processor (DSP) node
Represents the digital signal processor interface, designed to offload
audio related tasks.
- compatible : should be "nintendo,flipper-pic"
- interrupt-controller
-1.c) The Digital Signal Procesor (DSP) node
+1.c) The Digital Signal Processor (DSP) node
Represents the digital signal processor interface, designed to offload
audio related tasks.
The IP block has a version register so this can be used for detection
instead of having to encode the IP version number in the device tree
- comaptible.
+ compatible.
allOf:
- $ref: pwm.yaml#
nodes is defined using the standard binding for regulators found at
<Documentation/devicetree/bindings/regulator/regulator.txt>.
-Theres are also additional properties for SD/LDOs. These additional properties
+There are also additional properties for SD/LDOs. These additional properties
are required to configure FPS configuration parameters for SDs and LDOs.
Please refer <devicetree/bindings/mfd/max77620.txt> for more detail of Flexible
Power Sequence (FPS).
regulator-oc-error-microamp:
description: Set over current error limit. This is a limit where part of
- the hardware propably is malfunctional and damage prevention is requested.
+ the hardware probably is malfunctional and damage prevention is requested.
Zero can be passed to disable error detection and value '1' indicates
that detection should be enabled but limit setting can be omitted.
regulator-ov-error-microvolt:
description: Set over voltage error limit. This is a limit where part of
- the hardware propably is malfunctional and damage prevention is requested
+ the hardware probably is malfunctional and damage prevention is requested
Zero can be passed to disable error detection and value '1' indicates
that detection should be enabled but limit setting can be omitted. Limit
is given as microvolt offset from voltage set to regulator.
regulator-uv-error-microvolt:
description: Set under voltage error limit. This is a limit where part of
- the hardware propably is malfunctional and damage prevention is requested
+ the hardware probably is malfunctional and damage prevention is requested
Zero can be passed to disable error detection and value '1' indicates
that detection should be enabled but limit setting can be omitted. Limit
is given as microvolt offset from voltage set to regulator.
regulator-temp-error-kelvin:
description: Set over temperature error limit. This is a limit where part of
- the hardware propably is malfunctional and damage prevention is requested
+ the hardware probably is malfunctional and damage prevention is requested
Zero can be passed to disable error detection and value '1' indicates
that detection should be enabled but limit setting can be omitted.
description: |
The RT5190A integrates 1 channel buck controller, 3 channels high efficiency
- synchronous buck converters, 1 LDO, I2C control interface and peripherial
+ synchronous buck converters, 1 LDO, I2C control interface and peripheral
logical control.
It also supports mute AC OFF depop sound and quick setting storage while
margin from the expected value for a given control
voltage. On larger voltage decreases this can occur
undesiredly since the output voltage does not adjust
- inmediately to changes in the control voltage. To
+ immediately to changes in the control voltage. To
avoid this situation the vctrl driver breaks down
larger voltage decreases into multiple steps, where
each step is within the OVP threshold.
caches. Each of the TCMs can be enabled or disabled independently and
either of them can be configured to appear at that R5F's address 0x0.
- The cores do not use an MMU, but has a Region Address Translater
+ The cores do not use an MMU, but has a Region Address Translator
(RAT) module that is accessible only from the R5Fs for providing
translations between 32-bit CPU addresses into larger system bus
addresses. Cache and memory access settings are provided through a
Cell #6 : bit position of the reset in the
reset status register
Cell #7 : Flags used to control reset behavior,
- availible flags defined in the DT include
+ available flags defined in the DT include
file <dt-bindings/reset/ti-syscon.h>
SysCon Reset Consumer Nodes
clocks:
minItems: 1
items:
- - description: EIP150 gatable clock
- - description: Main gatable clock
+ - description: EIP150 gateable clock
+ - description: Main gateable clock
clock-names:
minItems: 1
- ctrl-reg : Contains the initial value of the control register also
called "Register B".
- freq-reg : Contains the initial value of the frequency register also
- called "Regsiter A".
+ called "Register A".
"Register A" and "B" are usually initialized by the firmware (BIOS for
instance). If this is not done, it can be performed by the driver.
Optional properties:
- st,hw-flow-ctrl bool flag to enable hardware flow control.
-- st,force-m1 bool flat to force asc to be in Mode-1 recommeded
+- st,force-m1 bool flat to force asc to be in Mode-1 recommended
for high bit rates (above 19.2K)
Example:
serial@fe440000{
description:
The MediaTek wo-ccif provides a configuration interface for WED WO
- controller used to perfrom offload rx packet processing (e.g. 802.11
+ controller used to perform offload rx packet processing (e.g. 802.11
aggregation packet reordering or rx header translation) on MT7986 soc.
properties:
description: |
PolarFire SoC devices include a microcontroller acting as the system controller,
which provides "services" to the main processor and to the FPGA fabric. These
- services include hardware rng, reprogramming of the FPGA and verfification of the
+ services include hardware rng, reprogramming of the FPGA and verification of the
eNVM contents etc. More information on these services can be found online, at
https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
description:
The AOSS side channel also provides the controls for three cooling devices,
these are expressed as subnodes of the QMP node. The name of the node is
- used to identify the resource and must therefor be "cx", "mx" or "ebi".
+ used to identify the resource and must therefore be "cx", "mx" or "ebi".
properties:
"#cooling-cells":
IN2 +---o--+------------+--o---+ OUT2
loop2 relays
-The 'loop1' gpio pin controlls two relays, which are either in loop position,
+The 'loop1' gpio pin controls two relays, which are either in loop position,
meaning that input and output are directly connected, or they are in mixer
position, meaning that the signal is passed through the 'Sum' mixer. Similarly
for 'loop2'.
See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet
- -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formating
+ -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formatting
on the I2S Port. Each of the 3 8 bit values in the array contain the settings
for depth, location, and frame.
one amplifier in the system. If more than one it is best to Hi-Z the ASP
port to prevent bus contention on the output signal
- - cirrus,boost-ctl-select : Boost conerter control source selection.
+ - cirrus,boost-ctl-select : Boost converter control source selection.
Selects the source of the BST_CTL target VBST voltage for the boost
converter to generate.
0x00 - Control Port Value
* frame using two different ways:
* 1) Normal I2S mode on two data pins -- each SDOUT
* carries 2-channel data in the same time.
- * 2) TDM mode on one signle data pin -- SDOUT1 carries
+ * 2) TDM mode on one single data pin -- SDOUT1 carries
* 4-channel data per frame.
Example:
- fsl,esai-synchronous: This is a boolean property. If present, indicating
that ESAI would work in the synchronous mode, which
means all the settings for Receiving would be
- duplicated from Transmition related registers.
+ duplicated from Transmission related registers.
Optional properties:
maxItems: 16
description:
This is a list of channel IDs which should be disabled.
- By default, all data received from ETDM pins will be outputed to
+ By default, all data received from ETDM pins will be outputted to
memory. etdm in supports disable_out in direct mode(w/o interconn),
so user can disable the specified channels by the property.
uniqueItems: true
Mediatek AFE PCM controller for mt2701
Required properties:
-- compatible: should be one of the followings.
+- compatible: should be one of the following.
- "mediatek,mt2701-audio"
- "mediatek,mt7622-audio"
- interrupts: should contain AFE and ASYS interrupts
$ref: /schemas/types.yaml#/definitions/uint32
description: |
etdm modules can share the same external clock pin. Specify
- which etdm clock source is required by this etdm in moudule.
+ which etdm clock source is required by this etdm in module.
enum:
- 0 # etdm1_in
- 1 # etdm2_in
$ref: /schemas/types.yaml#/definitions/uint32
description: |
etdm modules can share the same external clock pin. Specify
- which etdm clock source is required by this etdm out moudule.
+ which etdm clock source is required by this etdm out module.
enum:
- 0 # etdm1_in
- 1 # etdm2_in
[xx]ch [yy]ch
------> [CTU] -------->
-CTU can convert [xx]ch to [yy]ch, or exchange outputed channel.
+CTU can convert [xx]ch to [yy]ch, or exchange outputted channel.
CTU conversion needs matrix settings.
For more detail information, see below
source. For this driver the first string should always be
"Analog".
-Optionnal properties:
+Optional properties:
- rockchip,hp-en-gpios = The phandle of the GPIO that power up/down the
headphone (when the analog output is an headphone).
- rockchip,hp-det-gpios = The phandle of the GPIO that detects the headphone
If the value is 0, it means the impedance sensing is not supported.
- "realtek,impedance_sensing_table"
The matrix rows of the impedance sensing table are consisted by impedance
- minimum, impedance maximun, volume, DC offset w/o and w/ mic of each L and
+ minimum, impedance maximum, volume, DC offset w/o and w/ mic of each L and
R channel accordingly. Example is shown as following.
< 0 300 7 0xffd160 0xffd1c0 0xff8a10 0xff8ab0
301 65535 4 0xffe470 0xffe470 0xffb8e0 0xffb8e0>
parent serial device. If the standard MIDI baud of 31.25 kBaud is needed
(as would be the case if interfacing with arbitrary external MIDI devices),
configure the clocks of the parent serial device so that a requested baud of 38.4 kBaud
- resuts in the standard MIDI baud rate, and set the 'current-speed' property to 38400 (default)
+ results in the standard MIDI baud rate, and set the 'current-speed' property to 38400 (default)
properties:
compatible:
-* Spreadtrum DMA platfrom bindings
+* Spreadtrum DMA platform bindings
Required properties:
- compatible: Should be "sprd,pcm-platform".
additionalProperties: false
description:
Two subnodes corresponding to SAI sub-block instances A et B
- can be defined. Subnode can be omitted for unsused sub-block.
+ can be defined. Subnode can be omitted for unused sub-block.
properties:
compatible:
description: |
The Infotainment board plugs into the Common Processor Board, the support of the
- extension board is extending the CPB audio support, decribed in:
+ extension board is extending the CPB audio support, described in:
sound/ti,j721e-cpb-audio.txt
The audio support on the Infotainment Expansion Board consists of McASP0
reg:
description:
I2C address, in multiple tas2781s case, all the i2c address
- aggreate as one Audio Device to support multiple audio slots.
+ aggregate as one Audio Device to support multiple audio slots.
maxItems: 8
minItems: 1
items:
reg:
maxItems: 1
description: |
- I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
+ I2C address of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
reset-gpios:
maxItems: 1
qcom,ports-hstart:
$ref: /schemas/types.yaml#/definitions/uint8-array
description:
- Identifying lowerst numbered coloum in SoundWire Frame,
+ Identifying lowerst numbered column in SoundWire Frame,
i.e. left edge of the Transport sub-frame for each port.
Out ports followed by In ports.
Value of 0xff indicates that this option is not implemented
qcom,ports-hstop:
$ref: /schemas/types.yaml#/definitions/uint8-array
description:
- Identifying highest numbered coloum in SoundWire Frame,
+ Identifying highest numbered column in SoundWire Frame,
i.e. the right edge of the Transport
sub-frame for each port. Out ports followed by In ports.
Value of 0xff indicates that this option is not implemented
-Broadcom BCM2835 auxiliar SPI1/2 controller
+Broadcom BCM2835 auxiliary SPI1/2 controller
The BCM2835 contains two forms of SPI master controller, one known simply as
SPI0, and the other known as the "Universal SPI Master"; part of the
- reg: Should contain register location and length for the spi block
- interrupts: Should contain shared interrupt of the aux block
- clocks: The clock feeding the SPI controller - needs to
- point to the auxiliar clock driver of the bcm2835,
+ point to the auxiliary clock driver of the bcm2835,
as this clock will enable the output gate for the specific
clock.
- cs-gpios: the cs-gpios (native cs is NOT supported)
description: |
The Broadcom SPI controller is a SPI master found on various SOCs, including
- BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
+ BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
of:
MSPI : SPI master controller can read and write to a SPI slave device
BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
io with 3-byte and 4-byte addressing support.
Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
- MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance
+ MSPI master can be used without BSPI. BRCMSTB SoCs have an additional instance
of a MSPI master without the BSPI to use with non flash slave devices that
use SPI protocol.
dma-names:
description:
List of DMA request names. These strings correspond 1:1 with
- the DMA sepecifiers listed in dmas. The string names is to be
+ the DMA specifiers listed in dmas. The string names is to be
"rxN" and "txN" for RX and TX requests, respectively. Where N
is the chip select number.
minItems: 1
Synopsys ARC Local Timer with Interrupt Capabilities
- Found on all ARC CPUs (ARC700/ARCHS)
- Can be optionally programmed to interrupt on Limit
-- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
+- Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
TIMER0 used as clockevent provider (true for all ARC cores)
TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
- maxim,max1237
# Temperature Sensor, I2C interface
- maxim,max1619
- # 10-bit 10 kOhm linear programable voltage divider
+ # 10-bit 10 kOhm linear programmable voltage divider
- maxim,max5481
- # 10-bit 50 kOhm linear programable voltage divider
+ # 10-bit 50 kOhm linear programmable voltage divider
- maxim,max5482
- # 10-bit 10 kOhm linear programable variable resistor
+ # 10-bit 10 kOhm linear programmable variable resistor
- maxim,max5483
- # 10-bit 50 kOhm linear programable variable resistor
+ # 10-bit 50 kOhm linear programmable variable resistor
- maxim,max5484
# PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion
- maxim,max6621
at RTL is 0, so this property only affects siTD.
If this property is not set, the max packet size is 1023 bytes, and
- if the total of packet size for pervious transactions are more than
+ if the total of packet size for previous transactions are more than
256 bytes, it can't accept any transactions within this frame. The
use case is single transaction, but higher frame rate.
fsl,permanently-attached:
type: boolean
description:
- Indicates if the device atached to a downstream port is
+ Indicates if the device attached to a downstream port is
permanently attached.
fsl,disable-port-power-control:
- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
- switch-gpio: A phandle + gpio-specifier pair. Some boards are using Dual
- SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex
+ SPDT USB Switch, witch is controlled by GPIO to de/multiplex
D+/D- USB lines between connectors.
- qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
- ChiYuan Huang <cy_huang@richtek.com>
description: |
- The RT1719 is a sink-only USB Type-C contoller that complies with the latest
+ The RT1719 is a sink-only USB Type-C controller that complies with the latest
USB Type-C and PD standards. It does the USB Type-C detection including attach
and orientation. It integrates the physical layer of the USB BMC power
delivery protocol to allow up to 100W of power. The BMC PD block enables full
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