comment

llvm-svn: 157005

diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 41b4b71..1d810fd 100644 (file)
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -819,8 +819,6 @@ SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
     assert(TopQueue.empty() && BotQueue.empty() && "ReadyQ garbage");
     return NULL;
   }
-  // As an initial placeholder heuristic, schedule in the direction that has
-  // the fewest choices.
   SUnit *SU;
   if (ForceTopDown) {
     SU = DAG->getSUnit(DAG->top());

diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index fbd08cb..912ed0d 100644 (file)
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -698,7 +698,7 @@ getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta) {
       unsigned Reg = VirtRegOpers.Uses[i];
       const LiveInterval *LI = &LIS->getInterval(Reg);
       // FIXME: allow the caller to pass in the list of vreg uses that remain to
-      // be top-scheduled to avoid searching uses at each query.
+      // be bottom-scheduled to avoid searching uses at each query.
       SlotIndex CurrIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
       if (LI->killedAt(SlotIdx)
           && !findUseBetween(Reg, CurrIdx, SlotIdx, MRI, LIS)) {