}
InstructionCost RISCVTTIImpl::getVectorImmCost(VectorType *VecTy,
- TTI::OperandValueKind OpInfo,
- TTI::OperandValueProperties PropInfo,
+ TTI::OperandValueInfo OpInfo,
TTI::TargetCostKind CostKind) {
- assert((OpInfo == TTI::OK_UniformConstantValue ||
- OpInfo == TTI::OK_NonUniformConstantValue) && "non constant operand?");
+ assert(OpInfo.isConstant() && "non constant operand?");
APInt PseudoAddr = APInt::getAllOnes(DL.getPointerSizeInBits());
// Add a cost of address load + the cost of the vector load.
return RISCVMatInt::getIntMatCost(PseudoAddr, DL.getPointerSizeInBits(),
MaybeAlign Alignment,
unsigned AddressSpace,
TTI::TargetCostKind CostKind,
- TTI::OperandValueKind OpdInfo,
+ TTI::OperandValueKind OpdKind,
const Instruction *I) {
+ const TTI::OperandValueInfo OpInfo = {OpdKind, TTI::OP_None};
InstructionCost Cost = 0;
- if (Opcode == Instruction::Store && isa<VectorType>(Src) &&
- (OpdInfo == TTI::OK_UniformConstantValue ||
- OpdInfo == TTI::OK_NonUniformConstantValue)) {
- Cost += getVectorImmCost(cast<VectorType>(Src), OpdInfo, TTI::OP_None, CostKind);
- }
+ if (Opcode == Instruction::Store && isa<VectorType>(Src) && OpInfo.isConstant())
+ Cost += getVectorImmCost(cast<VectorType>(Src), OpInfo, CostKind);
return Cost + BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
- CostKind, OpdInfo, I);
+ CostKind, OpInfo.Kind, I);
}
void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
TTI::OperandValueProperties Opd1PropInfo,
TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
const Instruction *CxtI) {
+
+ const TTI::OperandValueInfo Op2Info = {Op2Kind, Opd2PropInfo};
+
// vXi8 multiplications are always promoted to vXi16.
if (Opcode == Instruction::Mul && Ty->isVectorTy() &&
Ty->getScalarSizeInBits() == 8) {
}
// Vector multiply by pow2 will be simplified to shifts.
- if (ISD == ISD::MUL &&
- (Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue) &&
- Opd2PropInfo == TargetTransformInfo::OP_PowerOf2)
+ if (ISD == ISD::MUL && Op2Info.isConstant() && Op2Info.isPowerOf2())
return getArithmeticInstrCost(Instruction::Shl, Ty, CostKind, Op1Kind,
Op2Kind, TargetTransformInfo::OP_None,
TargetTransformInfo::OP_None);
// The OperandValue properties may not be the same as that of the previous
// operation; conservatively assume OP_None.
if ((ISD == ISD::SDIV || ISD == ISD::SREM) &&
- (Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue) &&
- Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
+ Op2Info.isConstant() && Op2Info.isPowerOf2()) {
InstructionCost Cost =
2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Kind,
Op2Kind, TargetTransformInfo::OP_None,
// Vector unsigned division/remainder will be simplified to shifts/masks.
if ((ISD == ISD::UDIV || ISD == ISD::UREM) &&
- (Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue) &&
- Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
+ Op2Info.isConstant() && Op2Info.isPowerOf2()) {
if (ISD == ISD::UDIV)
return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Kind,
Op2Kind, TargetTransformInfo::OP_None,
{ ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb.
};
- if (Op2Kind == TargetTransformInfo::OK_UniformConstantValue &&
- ST->hasBWI()) {
+ if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasBWI()) {
if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD,
LT.second))
return LT.first * Entry->Cost;
{ ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence
};
- if (Op2Kind == TargetTransformInfo::OK_UniformConstantValue &&
- ST->hasAVX512()) {
+ if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX512()) {
if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD,
LT.second))
return LT.first * Entry->Cost;
{ ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence
};
- if (Op2Kind == TargetTransformInfo::OK_UniformConstantValue &&
- ST->hasAVX2()) {
+ if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX2()) {
if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD,
LT.second))
return LT.first * Entry->Cost;
};
// XOP has faster vXi8 shifts.
- if (Op2Kind == TargetTransformInfo::OK_UniformConstantValue &&
+ if (Op2Info.isUniform() && Op2Info.isConstant() &&
ST->hasSSE2() && !ST->hasXOP()) {
if (const auto *Entry =
CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
{ ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence
};
- if ((Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue) &&
- ST->hasBWI()) {
+ if (Op2Info.isConstant() && ST->hasBWI()) {
if (const auto *Entry =
CostTableLookup(AVX512BWConstCostTable, ISD, LT.second))
return LT.first * Entry->Cost;
{ ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence
};
- if ((Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue) &&
- ST->hasAVX512()) {
+ if (Op2Info.isConstant() && ST->hasAVX512()) {
if (const auto *Entry =
CostTableLookup(AVX512ConstCostTable, ISD, LT.second))
return LT.first * Entry->Cost;
{ ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence
};
- if ((Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue) &&
- ST->hasAVX2()) {
+ if (Op2Info.isConstant() && ST->hasAVX2()) {
if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second))
return LT.first * Entry->Cost;
}
{ ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence
};
- if ((Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue) &&
- ST->hasSSE2()) {
+ if (Op2Info.isConstant() && ST->hasSSE2()) {
// pmuldq sequence.
if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
return LT.first * 32;
{ ISD::SRL, MVT::v4i64, 1 }, // psrlq
};
- if (ST->hasAVX2() &&
- ((Op2Kind == TargetTransformInfo::OK_UniformConstantValue) ||
- (Op2Kind == TargetTransformInfo::OK_UniformValue))) {
+ if (ST->hasAVX2() && Op2Info.isUniform()) {
if (const auto *Entry =
CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
return LT.first * Entry->Cost;
{ ISD::SRA, MVT::v4i32, 1 }, // psrad.
};
- if (ST->hasSSE2() &&
- ((Op2Kind == TargetTransformInfo::OK_UniformConstantValue) ||
- (Op2Kind == TargetTransformInfo::OK_UniformValue))) {
+ if (ST->hasSSE2() && Op2Info.isUniform()) {
if (const auto *Entry =
CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
return LT.first * Entry->Cost;
};
if (ST->hasAVX512()) {
- if (ISD == ISD::SHL && LT.second == MVT::v32i16 &&
- (Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue))
+ if (ISD == ISD::SHL && LT.second == MVT::v32i16 && Op2Info.isConstant())
// On AVX512, a packed v32i16 shift left by a constant build_vector
// is lowered into a vector multiply (vpmullw).
return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
// Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts).
if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) {
if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
- (Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue))
+ Op2Info.isConstant())
// On AVX2, a packed v16i16 shift left by a constant build_vector
// is lowered into a vector multiply (vpmullw).
return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
// If the right shift is constant then we'll fold the negation so
// it's as cheap as a left shift.
int ShiftISD = ISD;
- if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) &&
- (Op2Kind == TargetTransformInfo::OK_UniformConstantValue ||
- Op2Kind == TargetTransformInfo::OK_NonUniformConstantValue))
+ if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && Op2Info.isConstant())
ShiftISD = ISD::SHL;
if (const auto *Entry =
CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second))
{ ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split.
};
- if (ST->hasSSE2() &&
- ((Op2Kind == TargetTransformInfo::OK_UniformConstantValue) ||
- (Op2Kind == TargetTransformInfo::OK_UniformValue))) {
+ if (ST->hasSSE2() && Op2Info.isUniform()) {
// Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table.
if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2())
MaybeAlign Alignment,
unsigned AddressSpace,
TTI::TargetCostKind CostKind,
- TTI::OperandValueKind OpdInfo,
+ TTI::OperandValueKind OpdKind,
const Instruction *I) {
+ const TTI::OperandValueInfo OpInfo = {OpdKind, TTI::OP_None};
+
// TODO: Handle other cost kinds.
if (CostKind != TTI::TCK_RecipThroughput) {
if (auto *SI = dyn_cast_or_null<StoreInst>(I)) {
InstructionCost Cost = 0;
// Add a cost for constant load to vector.
- if (Opcode == Instruction::Store &&
- (OpdInfo == TTI::OK_UniformConstantValue ||
- OpdInfo == TTI::OK_NonUniformConstantValue))
+ if (Opcode == Instruction::Store && OpInfo.isConstant())
Cost += getMemoryOpCost(Instruction::Load, Src, DL.getABITypeAlign(Src),
/*AddressSpace=*/0, CostKind);