clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses
authorMarc Zyngier <maz@kernel.org>
Sun, 17 Oct 2021 12:42:09 +0000 (13:42 +0100)
committerDaniel Lezcano <daniel.lezcano@linaro.org>
Sun, 17 Oct 2021 19:45:48 +0000 (21:45 +0200)
As we are about to change the registers that are used by the driver,
start by adding build-time checks to ensure that we always handle
all registers and access modes.

Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-2-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
arch/arm/include/asm/arch_timer.h
arch/arm64/include/asm/arch_timer.h
drivers/clocksource/arm_arch_timer.c

index 9917581..a5d27cf 100644 (file)
@@ -34,6 +34,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
                case ARCH_TIMER_REG_TVAL:
                        asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
                        break;
+               default:
+                       BUILD_BUG();
                }
        } else if (access == ARCH_TIMER_VIRT_ACCESS) {
                switch (reg) {
@@ -43,7 +45,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
                case ARCH_TIMER_REG_TVAL:
                        asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
                        break;
+               default:
+                       BUILD_BUG();
                }
+       } else {
+               BUILD_BUG();
        }
 
        isb();
@@ -62,6 +68,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
                case ARCH_TIMER_REG_TVAL:
                        asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
                        break;
+               default:
+                       BUILD_BUG();
                }
        } else if (access == ARCH_TIMER_VIRT_ACCESS) {
                switch (reg) {
@@ -71,7 +79,11 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
                case ARCH_TIMER_REG_TVAL:
                        asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
                        break;
+               default:
+                       BUILD_BUG();
                }
+       } else {
+               BUILD_BUG();
        }
 
        return val;
index 88d20f0..fa12ea4 100644 (file)
@@ -112,6 +112,8 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
                case ARCH_TIMER_REG_TVAL:
                        write_sysreg(val, cntp_tval_el0);
                        break;
+               default:
+                       BUILD_BUG();
                }
        } else if (access == ARCH_TIMER_VIRT_ACCESS) {
                switch (reg) {
@@ -121,7 +123,11 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
                case ARCH_TIMER_REG_TVAL:
                        write_sysreg(val, cntv_tval_el0);
                        break;
+               default:
+                       BUILD_BUG();
                }
+       } else {
+               BUILD_BUG();
        }
 
        isb();
@@ -136,6 +142,8 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
                        return read_sysreg(cntp_ctl_el0);
                case ARCH_TIMER_REG_TVAL:
                        return arch_timer_reg_read_stable(cntp_tval_el0);
+               default:
+                       BUILD_BUG();
                }
        } else if (access == ARCH_TIMER_VIRT_ACCESS) {
                switch (reg) {
@@ -143,10 +151,13 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
                        return read_sysreg(cntv_ctl_el0);
                case ARCH_TIMER_REG_TVAL:
                        return arch_timer_reg_read_stable(cntv_tval_el0);
+               default:
+                       BUILD_BUG();
                }
        }
 
-       BUG();
+       BUILD_BUG();
+       unreachable();
 }
 
 static inline u32 arch_timer_get_cntfrq(void)
index be6d741..3b7d46d 100644 (file)
@@ -112,6 +112,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
                case ARCH_TIMER_REG_TVAL:
                        writel_relaxed(val, timer->base + CNTP_TVAL);
                        break;
+               default:
+                       BUILD_BUG();
                }
        } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
                struct arch_timer *timer = to_arch_timer(clk);
@@ -122,6 +124,8 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
                case ARCH_TIMER_REG_TVAL:
                        writel_relaxed(val, timer->base + CNTV_TVAL);
                        break;
+               default:
+                       BUILD_BUG();
                }
        } else {
                arch_timer_reg_write_cp15(access, reg, val);
@@ -143,6 +147,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
                case ARCH_TIMER_REG_TVAL:
                        val = readl_relaxed(timer->base + CNTP_TVAL);
                        break;
+               default:
+                       BUILD_BUG();
                }
        } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
                struct arch_timer *timer = to_arch_timer(clk);
@@ -153,6 +159,8 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
                case ARCH_TIMER_REG_TVAL:
                        val = readl_relaxed(timer->base + CNTV_TVAL);
                        break;
+               default:
+                       BUILD_BUG();
                }
        } else {
                val = arch_timer_reg_read_cp15(access, reg);