arm64: dts: qcom: sc7180: align MPSS PAS node with bindings

The SC7180 MPSS/MSS remote processor can be brought to life using two
different bindings:
1. qcom,sc7180-mpss-pas - currently used in DTSI
2. qcom,sc7180-mss-pil

Move the properties related to qcom,sc7180-mss-pil (qcom,halt-regs,
qcom,spare-regs, resets, additional clocks and regs) to specific boards
using the PIL, to silence DT schema warnings.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221124184333.133911-4-krzysztof.kozlowski@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 70fd9ff8dfa214a04bf4b476f48fd87d8d5ddb65..b27b5f0e2b6b2dda81214043b8a27f25cc96e70a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -370,8 +370,26 @@
 &remoteproc_mpss {
        status = "okay";
        compatible = "qcom,sc7180-mss-pil";
+       reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
+       reg-names = "qdsp6", "rmb";
+
+       clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+                <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+                <&gcc GCC_MSS_NAV_AXI_CLK>,
+                <&gcc GCC_MSS_SNOC_AXI_CLK>,
+                <&gcc GCC_MSS_MFAB_AXIS_CLK>,
+                <&rpmhcc RPMH_CXO_CLK>;
+       clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo";
+
        iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>;
        memory-region = <&mba_mem &mpss_mem>;
+
+       resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
+                <&pdc_reset PDC_MODEM_SYNC_RESET>;
+       reset-names = "mss_restart", "pdc_reset";
+
+       qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
+       qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
 };
 
 &sdhc_1 {

diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index f1defb94d6702d095af5080c6f324dba51c54c82..d134d172a3c520f5354ec097bae524ce17faa8fc 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -853,12 +853,30 @@ hp_i2c: &i2c9 {
 &remoteproc_mpss {
        status = "okay";
        compatible = "qcom,sc7180-mss-pil";
+       reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
+       reg-names = "qdsp6", "rmb";
+
+       clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+                <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+                <&gcc GCC_MSS_NAV_AXI_CLK>,
+                <&gcc GCC_MSS_SNOC_AXI_CLK>,
+                <&gcc GCC_MSS_MFAB_AXIS_CLK>,
+                <&rpmhcc RPMH_CXO_CLK>;
+       clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo";
+
        iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>;
        memory-region = <&mba_mem &mpss_mem>;
 
        /* This gets overridden for SKUs with LTE support. */
        firmware-name = "qcom/sc7180-trogdor/modem-nolte/mba.mbn",
                        "qcom/sc7180-trogdor/modem-nolte/qdsp6sw.mbn";
+
+       resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
+                <&pdc_reset PDC_MODEM_SYNC_RESET>;
+       reset-names = "mss_restart", "pdc_reset";
+
+       qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
+       qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
 };
 
 &sdhc_1 {

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index f71cf21a8dd8a67673024b9b96e1ff4869993cbd..23f5920fba2d2077f9a88fa26297004102863892 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1929,8 +1929,7 @@
 
                remoteproc_mpss: remoteproc@4080000 {
                        compatible = "qcom,sc7180-mpss-pas";
-                       reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
-                       reg-names = "qdsp6", "rmb";
+                       reg = <0 0x04080000 0 0x4040>;
 
                        interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
                                              <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1941,14 +1940,8 @@
                        interrupt-names = "wdog", "fatal", "ready", "handover",
                                          "stop-ack", "shutdown-ack";
 
-                       clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
-                                <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
-                                <&gcc GCC_MSS_NAV_AXI_CLK>,
-                                <&gcc GCC_MSS_SNOC_AXI_CLK>,
-                                <&gcc GCC_MSS_MFAB_AXIS_CLK>,
-                                <&rpmhcc RPMH_CXO_CLK>;
-                       clock-names = "iface", "bus", "nav", "snoc_axi",
-                                     "mnoc_axi", "xo";
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "xo";
 
                        power-domains = <&rpmhpd SC7180_CX>,
                                        <&rpmhpd SC7180_MX>,
@@ -1962,13 +1955,6 @@
                        qcom,smem-states = <&modem_smp2p_out 0>;
                        qcom,smem-state-names = "stop";
 
-                       resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
-                                <&pdc_reset PDC_MODEM_SYNC_RESET>;
-                       reset-names = "mss_restart", "pdc_reset";
-
-                       qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
-                       qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
-
                        status = "disabled";
 
                        glink-edge {