ARM: socfpga: Sort the DT Makefile
authorMarek Vasut <marex@denx.de>
Mon, 7 May 2018 20:29:17 +0000 (22:29 +0200)
committerMarek Vasut <marex@denx.de>
Fri, 18 May 2018 08:30:46 +0000 (10:30 +0200)
Sort the Makefile entries, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
arch/arm/dts/Makefile

index 7bec3d6..2af94da 100644 (file)
@@ -183,20 +183,20 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=                          \
-       socfpga_arria10_socdk_sdmmc.dtb                 \
        socfpga_arria5_socdk.dtb                        \
+       socfpga_arria10_socdk_sdmmc.dtb                 \
        socfpga_cyclone5_is1.dtb                        \
        socfpga_cyclone5_mcvevk.dtb                     \
        socfpga_cyclone5_socdk.dtb                      \
        socfpga_cyclone5_dbm_soc1.dtb                   \
-       socfpga_cyclone5_de0_nano_soc.dtb                       \
+       socfpga_cyclone5_de0_nano_soc.dtb               \
        socfpga_cyclone5_de1_soc.dtb                    \
        socfpga_cyclone5_de10_nano.dtb                  \
        socfpga_cyclone5_sockit.dtb                     \
        socfpga_cyclone5_socrates.dtb                   \
        socfpga_cyclone5_sr1500.dtb                     \
-       socfpga_stratix10_socdk.dtb                     \
-       socfpga_cyclone5_vining_fpga.dtb
+       socfpga_cyclone5_vining_fpga.dtb                \
+       socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
        dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb