arm: socfpga: gen5: remove hacked ETH RST handling

The 'dwmac_socfpga' ETH driver can now get the MACs out of reset
via the socfpga reset driver and can set PHY mode via syscon.

This means we can now remove the ad-hoc code to do this from
arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index d9e0b33..42beaec 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -10,8 +10,6 @@ void reset_cpu(ulong addr);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
-int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
-                                            const u8 phymode));
 
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
 

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 78fbe28..e1adea1 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -120,71 +120,6 @@ int arch_cpu_init(void)
        return 0;
 }
 
-#ifdef CONFIG_ETH_DESIGNWARE
-static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
-       if (!phymode)
-               return -EINVAL;
-
-       if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
-               *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
-               return 0;
-       }
-
-       if (!strcmp(phymode, "rgmii")) {
-               *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
-               return 0;
-       }
-
-       if (!strcmp(phymode, "rmii")) {
-               *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
-               return 0;
-       }
-
-       return -EINVAL;
-}
-
-int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
-                                            const u8 phymode))
-{
-       const void *fdt = gd->fdt_blob;
-       struct fdtdec_phandle_args args;
-       const char *phy_mode;
-       u32 phy_modereg;
-       int nodes[2];   /* Max. two GMACs */
-       int ret, count;
-       int i, node;
-
-       count = fdtdec_find_aliases_for_id(fdt, "ethernet",
-                                          COMPAT_ALTERA_SOCFPGA_DWMAC,
-                                          nodes, ARRAY_SIZE(nodes));
-       for (i = 0; i < count; i++) {
-               node = nodes[i];
-               if (node <= 0)
-                       continue;
-
-               ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
-                                                    "#reset-cells", 1, 0,
-                                                    &args);
-               if (ret || (args.args_count != 1)) {
-                       debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
-                       continue;
-               }
-
-               phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
-               ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
-               if (ret) {
-                       debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
-                       continue;
-               }
-
-               resetfn(args.args[0], phy_modereg);
-       }
-
-       return 0;
-}
-#endif
-
 #ifndef CONFIG_SPL_BUILD
 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {

diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 04f237d..6e11ba6 100644 (file)
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -54,48 +54,6 @@ static Altera_desc altera_fpga[] = {
        },
 };
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode)
-{
-       u32 physhift, reset;
-
-       if (of_reset_id == EMAC0_RESET) {
-               physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
-               reset = SOCFPGA_RESET(EMAC0);
-       } else if (of_reset_id == EMAC1_RESET) {
-               physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
-               reset = SOCFPGA_RESET(EMAC1);
-       } else {
-               printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
-               return;
-       }
-
-       /* configure to PHY interface select choosed */
-       clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
-                       SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
-                       phymode << physhift);
-
-       /* Release the EMAC controller from reset */
-       socfpga_per_reset(reset, 0);
-}
-
-static int socfpga_eth_reset(void)
-{
-       /* Put all GMACs into RESET state. */
-       socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
-       socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-       return socfpga_eth_reset_common(gen5_dwmac_reset);
-};
-#else
-static int socfpga_eth_reset(void)
-{
-       return 0;
-};
-#endif
-
 static const struct {
        const u16       pn;
        const char      *name;
@@ -178,7 +136,7 @@ int arch_misc_init(void)
        env_set("bootmode", bsel_str[bsel].mode);
        if (fpga_id >= 0)
                env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
-       return socfpga_eth_reset();
+       return 0;
 }
 #endif