drm/amd/powerplay: fix thermal interrupts on vega10

a bug in programming thermal interrupt register masks out
interrupts and driver cannot receive interrupts. Setting
0 to mask bits will fix it.

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index 7491163..eb6e965 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -409,7 +409,9 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-       val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+       val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
+                       (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
+                       (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
 
        cgs_write_register(hwmgr->device, reg, val);