setb(mem_base, DMA_NUM_WR_BURST, threshold - 1);
setb(mem_base, DMA_RX_FIFO_TH, threshold - 1);
}
- setb(mem_base, CON_XCH, 1);
spicc->remain -= bl;
spicc->burst_len = bl;
+ if (spicc->irq)
+ enable_irq(spicc->irq);
+ setb(mem_base, CON_XCH, 1);
}
}
spicc_set_txfifo(spicc, dat);
}
setb(mem_base, CON_BURST_LEN, spicc->burst_len - 1);
- setb(mem_base, CON_XCH, 1);
spicc->remain -= spicc->burst_len;
+ if (spicc->irq)
+ enable_irq(spicc->irq);
+ setb(mem_base, CON_XCH, 1);
}
}
unsigned long flags;
spin_lock_irqsave(&spicc->lock, flags);
+ disable_irq_nosync(spicc->irq);
spicc_wait_complete(spicc, 100);
spicc_log(spicc, &spicc->remain, 1, XFER_COMP_ISR);
if (!spicc_get_flag(spicc, FLAG_DMA_EN))
spicc_log(spicc, &spicc->remain, 1, DMA_BEGIN);
if (spicc->irq) {
setb(mem_base, INT_XFER_COM_EN, 1);
- enable_irq(spicc->irq);
dma_one_burst(spicc);
ret = wait_for_completion_interruptible_timeout(
&spicc->completion, msecs_to_jiffies(2000));
- disable_irq_nosync(spicc->irq);
setb(mem_base, INT_XFER_COM_EN, 0);
} else {
while (spicc->remain) {
spicc_log(spicc, &spicc->remain, 1, PIO_BEGIN);
if (spicc->irq) {
setb(mem_base, INT_XFER_COM_EN, 1);
- enable_irq(spicc->irq);
pio_one_burst_send(spicc);
ret = wait_for_completion_interruptible_timeout(
&spicc->completion, msecs_to_jiffies(2000));
- disable_irq_nosync(spicc->irq);
setb(mem_base, INT_XFER_COM_EN, 0);
} else {
while (spicc->remain) {
u8 *tx_buf;
u8 *rx_buf;
unsigned int bytes_per_word;
+ unsigned int speed_hz;
unsigned long tx_remain;
unsigned long txb_remain;
unsigned long rx_remain;
cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
hz = clk_get_rate(spicc->clk);
- if (hz >= 100000000)
+ if (spicc->message->spi->mode & SPI_LOOP)
+ cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
+ else if (hz >= 100000000)
cap_delay = SPICC_CAP_DELAY_1_CYCLE;
else if (hz >= 80000000)
cap_delay = SPICC_CAP_NO_DELAY;
if (conf != conf_orig)
writel_relaxed(conf, spicc->base + SPICC_CONREG);
- clk_set_rate(spicc->clk, xfer->speed_hz);
+ if (spicc->speed_hz != xfer->speed_hz) {
+ spicc->speed_hz = xfer->speed_hz;
+ clk_set_rate(spicc->clk, xfer->speed_hz);
+ }
meson_spicc_auto_io_delay(spicc);
spicc->using_dma = 0;