.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
};
+static struct clksrc_clk clk_pclk = {
+ .clk = {
+ .name = "clk_pclk",
+ .id = -1,
+ .parent = &clk_hclk.clk,
+ },
+ .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
+};
+
int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
&clk_dout_mpll,
&clk_armclk,
&clk_hclk,
+ &clk_pclk,
};
void __init_or_cpufreq s5p6440_setup_clocks(void)
fclk = clk_get_rate(&clk_armclk.clk);
hclk = clk_get_rate(&clk_hclk.clk);
- pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK);
+ pclk = clk_get_rate(&clk_pclk.clk);
if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) {
/* Asynchronous mode */