media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values

Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2
register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT
flag value.
The vendor code does the same to set these values.
This fixes conformance test CAINIT_G_SHARP_3.

Fluster HEVC score is increase by one with this patch.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
index 34da4bf943a488ae9b56bafd5e065bbc20bf9806..5df6f08e26f52c0c799f48a211103c4c274ed856 100644 (file)
--- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
@@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx)
                hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
        }
 
-       if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) {
-               hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
-               hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
-       } else {
-               hantro_reg_write(vpu, &g2_cb_qp_offset, 0);
-               hantro_reg_write(vpu, &g2_cr_qp_offset, 0);
-       }
+       hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
+       hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
 
        hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
        hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);