clk:starfive:Change some clocks to 'ignore-unused'
authorxingyu.wu <xingyu.wu@starfivetech.com>
Tue, 17 May 2022 02:01:23 +0000 (10:01 +0800)
committerxingyu.wu <xingyu.wu@starfivetech.com>
Tue, 17 May 2022 02:12:05 +0000 (10:12 +0800)
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
drivers/clk/starfive/clk-starfive-jh7110-aon.c
drivers/clk/starfive/clk-starfive-jh7110-isp.c
drivers/clk/starfive/clk-starfive-jh7110-stg.c
drivers/clk/starfive/clk-starfive-jh7110-sys.c

index 54f9f17..737ecfe 100755 (executable)
@@ -46,11 +46,11 @@ static const struct jh7110_clk_data jh7110_clk_aon_data[] __initconst = {
        //otpc
        JH7110_GATE(JH7110_OTPC_CLK_APB,
                        "u0_otpc_clk_apb",
-                       GATE_FLAG_NORMAL, JH7110_AON_APB),
+                       CLK_IGNORE_UNUSED, JH7110_AON_APB),
        //rtc
        JH7110_GATE(JH7110_RTC_HMS_CLK_APB,
                        "u0_rtc_hms_clk_apb",
-                       GATE_FLAG_NORMAL, JH7110_AON_APB),
+                       CLK_IGNORE_UNUSED, JH7110_AON_APB),
        JH7110__DIV(JH7110_RTC_INTERNAL,
                        "rtc_internal", 1022, JH7110_OSC),
        JH7110__MUX(JH7110_RTC_HMS_CLK_OSC32K,
index 2fc7a28..bab16b6 100755 (executable)
@@ -40,17 +40,17 @@ static const struct jh7110_clk_data jh7110_clk_isp_data[] __initconst = {
        JH7110__DIV(JH7110_U0_M31DPHY_TXCLKESC_LAN0, "u0_m31dphy_txclkesc_lan0",
                        60, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
        JH7110_GATE(JH7110_U0_VIN_PCLK, "u0_vin_pclk",
-                       GATE_FLAG_NORMAL, JH7110_DOM4_APB),
+                       CLK_IGNORE_UNUSED, JH7110_DOM4_APB),
        JH7110__DIV(JH7110_U0_VIN_SYS_CLK, "u0_vin_sys_clk",
                        8, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
        JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF0, "u0_vin_pixel_clk_if0",
-                       GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
+                       CLK_IGNORE_UNUSED, JH7110_MIPI_RX0_PXL),
        JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF1, "u0_vin_pixel_clk_if1",
-                       GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
+                       CLK_IGNORE_UNUSED, JH7110_MIPI_RX0_PXL),
        JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF2, "u0_vin_pixel_clk_if2",
-                       GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
+                       CLK_IGNORE_UNUSED, JH7110_MIPI_RX0_PXL),
        JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF3, "u0_vin_pixel_clk_if3",
-                       GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
+                       CLK_IGNORE_UNUSED, JH7110_MIPI_RX0_PXL),
        JH7110__MUX(JH7110_U0_VIN_CLK_P_AXIWR, "u0_vin_clk_p_axiwr",
                        PARENT_NUMS_2,
                        JH7110_MIPI_RX0_PXL,
@@ -58,7 +58,7 @@ static const struct jh7110_clk_data jh7110_clk_isp_data[] __initconst = {
        //ispv2_top_wrapper
        JH7110_GMUX(JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C,
                        "u0_ispv2_top_wrapper_clk_c",
-                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
+                       CLK_IGNORE_UNUSED, PARENT_NUMS_2,
                        JH7110_MIPI_RX0_PXL,
                        JH7110_DVP_INV),
 };
index 477df78..2c151ce 100755 (executable)
@@ -45,7 +45,7 @@ static const struct jh7110_clk_data jh7110_clk_stg_data[] __initconst = {
        JH7110_GATE(JH7110_PCIE1_CLK_TL, "u1_plda_pcie_clk_tl",
                        GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_PCIE01_SLV_DEC_MAINCLK, "u0_pcie01_slv_dec_mainclk",
-                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
+                       CLK_IGNORE_UNUSED, JH7110_STG_AXIAHB),
        //security
        JH7110_GATE(JH7110_SEC_HCLK, "u0_sec_top_hclk",
                        GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
index 3bdcab5..8318966 100755 (executable)
@@ -52,11 +52,11 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        JH7110_PLL2_OUT,
                        JH7110_PLL1_OUT),
        JH7110__DIV(JH7110_ISP_AXI, "isp_axi", 4, JH7110_ISP_2X),
-       JH7110_GDIV(JH7110_GCLK0, "gclk0", GATE_FLAG_NORMAL,
+       JH7110_GDIV(JH7110_GCLK0, "gclk0", CLK_IGNORE_UNUSED,
                        62, JH7110_PLL0_DIV2),
-       JH7110_GDIV(JH7110_GCLK1, "gclk1", GATE_FLAG_NORMAL,
+       JH7110_GDIV(JH7110_GCLK1, "gclk1", CLK_IGNORE_UNUSED,
                        62, JH7110_PLL1_DIV2),
-       JH7110_GDIV(JH7110_GCLK2, "gclk2", GATE_FLAG_NORMAL,
+       JH7110_GDIV(JH7110_GCLK2, "gclk2", CLK_IGNORE_UNUSED,
                        62, JH7110_PLL2_DIV2),
        /*u0_u7mc_sft7110*/
        JH7110_GATE(JH7110_U7_CORE_CLK, "u0_u7mc_sft7110_core_clk",
@@ -173,9 +173,9 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        JH7110_GATE(JH7110_WAVE511_CLK_APB, "u0_WAVE511_clk_apb",
                        GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_VDEC_JPG_ARB_JPGCLK, "u0_vdec_jpg_arb_jpgclk",
-                       GATE_FLAG_NORMAL, JH7110_JPEGC_AXI),
+                       CLK_IGNORE_UNUSED, JH7110_JPEGC_AXI),
        JH7110_GATE(JH7110_VDEC_JPG_ARB_MAINCLK, "u0_vdec_jpg_arb_mainclk",
-                       GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
+                       CLK_IGNORE_UNUSED, JH7110_VDEC_AXI),
        JH7110_GATE(JH7110_NOC_BUS_CLK_VDEC_AXI,
                        "u0_sft7110_noc_bus_clk_vdec_axi",
                        GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
@@ -264,11 +264,11 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        GATE_FLAG_NORMAL, JH7110_GMAC0_GTXCLK),
        //SYS MISC
        JH7110_GATE(JH7110_SYS_IOMUX_PCLK, "u0_sys_iomux_pclk",
-                       GATE_FLAG_NORMAL, JH7110_APB12),
+                       CLK_IGNORE_UNUSED, JH7110_APB12),
        JH7110_GATE(JH7110_MAILBOX_CLK_APB, "u0_mailbox_clk_apb",
-                       GATE_FLAG_NORMAL, JH7110_APB12),
+                       CLK_IGNORE_UNUSED, JH7110_APB12),
        JH7110_GATE(JH7110_INT_CTRL_CLK_APB, "u0_int_ctrl_clk_apb",
-                       GATE_FLAG_NORMAL, JH7110_APB12),
+                       CLK_IGNORE_UNUSED, JH7110_APB12),
        //CAN
        JH7110_GATE(JH7110_CAN0_CTRL_CLK_APB, "u0_can_ctrl_clk_apb",
                        GATE_FLAG_NORMAL, JH7110_APB12),