static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
{
struct sh_eth_info *port_info = ð->port_info[eth->port];
+ unsigned long edmr;
/* Configure e-dmac registers */
- sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
- (EMDR_DESC | EDMR_EL), EDMR);
+ edmr = sh_eth_read(port_info, EDMR);
+ edmr &= ~EMDR_DESC_R;
+ edmr |= EMDR_DESC | EDMR_EL;
+#if defined(CONFIG_R8A77980)
+ edmr |= EDMR_NBST;
+#endif
+ sh_eth_write(port_info, edmr, EDMR);
sh_eth_write(port_info, 0, EESIPR);
sh_eth_write(port_info, 0, TRSCER);
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
#endif
}
sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(port_info, 1, RTRATE);
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
{ .compatible = "renesas,ether-r8a7791" },
{ .compatible = "renesas,ether-r8a7793" },
{ .compatible = "renesas,ether-r8a7794" },
+ { .compatible = "renesas,gether-r8a77980" },
{ }
};
#elif defined(CONFIG_R7S72100)
#define SH_ETH_TYPE_RZ
#define BASE_IO_ADDR 0xE8203000
+#elif defined(CONFIG_R8A77980)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR 0xE7400000
#endif
/*
/* EDMR */
enum DMAC_M_BIT {
+ EDMR_NBST = 0x80, /* DMA transfer burst mode */
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
EDMR_SRST = 0x03, /* Receive/Send reset */
ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980)
ECMR_RTM = 0x00000004,
#endif