drm/amd/display: Add dcn3.01 support to DM

Update dm for vangogh support.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5773816..41f50d4 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -100,6 +100,10 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 #endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
+#endif
 
 #define FIRMWARE_RAVEN_DMCU            "amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1172,6 +1176,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
 #endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+       case CHIP_VANGOGH:
+#endif
                return 0;
        case CHIP_NAVI12:
                fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1278,6 +1285,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
                fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
                break;
 #endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+       case CHIP_VANGOGH:
+               dmub_asic = DMUB_ASIC_DCN301;
+               fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
+               break;
+#endif
 
        default:
                /* ASIC doesn't support DMUB. */
@@ -3400,6 +3413,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
 #endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+       case CHIP_VANGOGH:
+#endif
                if (dcn10_register_irq_handlers(dm->adev)) {
                        DRM_ERROR("DM: Failed to initialize IRQ\n");
                        goto fail;
@@ -3573,6 +3589,13 @@ static int dm_early_init(void *handle)
                adev->mode_info.num_hpd = 6;
                adev->mode_info.num_dig = 6;
                break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+       case CHIP_VANGOGH:
+               adev->mode_info.num_crtc = 4;
+               adev->mode_info.num_hpd = 4;
+               adev->mode_info.num_dig = 4;
+               break;
+#endif
        case CHIP_NAVI14:
                adev->mode_info.num_crtc = 5;
                adev->mode_info.num_hpd = 5;
@@ -3893,6 +3916,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
                adev->asic_type == CHIP_SIENNA_CICHLID ||
                adev->asic_type == CHIP_NAVY_FLOUNDER ||
 #endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+               adev->asic_type == CHIP_VANGOGH ||
+#endif
            adev->asic_type == CHIP_RENOIR ||
            adev->asic_type == CHIP_RAVEN) {
                /* Fill GFX9 params */